Space ASIC Physical Design Engineer – SoC

Amazon; San Diego (CA); On-site; USD 154,000 - 215,000; Full time

Benefits offered by this job

Health insurance

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior ASIC physical design engineer to drive architectural feasibility, perform synthesis and place-and-route, and lead low-power design methods using UPF and AI-enabled flows. The role requires 5+ years in ASIC implementation, a B.S.

in EE or related field (M.S. preferred), and experience with RF/Analog/Mixed-signal blocks and multi-site collaboration.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of experience in ASIC implementation, including synthesis, STA and DFT for deep sub-micron nodes.
• Master's degree in Electrical or Communications Engineering or a related field.
• 7+ years of experience in ASIC implementation.
• Experience integrating RF/Analog/Mixed-signal blocks with digital top flows.
• Strong exposure to UPF flow for low power design.
• Experience working in multi-site/multi-team environments.
• Experience using managed ML/AI solutions.

Responsibilities

• Work with RTL/logic designers to drive architectural feasibility studies and power/performance/area tradeoffs.
• Drive IO/Core block physical implementation through synthesis, floor planning, place and route, and timing closure.
• Develop physical design methodologies while embracing AI flow.
• Evaluate 3rd party IP and provide recommendations.
• Collaborate with physical design engineers and RTL/Arch teams as a highly valued team member.

Skills

ASIC implementation

Synthesis/STA/DFT

Managed ML/AI solutions

Multi-site collaboration

RF/Analog/Mixed-signal integration

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical or Communications Engineering or related field

Tools

UPF flow for low power design

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior ASIC physical design engineer to drive architectural feasibility, perform synthesis and place-and-route, and lead low-power design methods using UPF and AI-enabled flows. The role requires 5+ years in ASIC implementation, a B.S.

in EE or related field (M.S. preferred), and experience with RF/Analog/Mixed-signal blocks and multi-site collaboration.