Senior ASIC Physical Design Engineer – AI-Driven SoC

Amazon Inc.; Austin (TX); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Leo is seeking a Sr. Physical Design Engineer to drive architectural feasibility and physical implementation for SOCs used in satellite communications. You will collaborate with RTL/Arch teams, optimize power, area, and performance, and guide P&R closure across multi-site teams.

The role emphasizes strong experience in ASIC implementation, UPF flows for low power design, and integration of RF/Analog/Mixed-signal blocks with digital top flows. A Master's and 10+ years are preferred.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 7+ years of ASIC implementation experience (synthesis, STA, DFT, P&R for deep sub-micron nodes).
• Preferred: Master's degree in Electrical or Communications Engineering or related field; 10+ years experience; RF/Analog/Mixed-signal integration with digital top flows; ML/AI solutions.

Responsibilities

• Collaborate with RTL/logic designers to study feasibility and tradeoffs for physical design closure.
• Lead IO/Core block physical implementation through synthesis, floor planning, pin planning, P&R, power/clock distribution, timing, ECOs, sign-off.
• Develop physical design methodologies with AI/ML flows.
• Evaluate third-party IP and provide recommendations.
• Work with cross-site teams and multi-disciplinary groups to ensure integrated design flows.

Skills

ASIC design

Synthesis

Floor planning

Place & Route

DFT

Power optimization

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or Communications Engineering

Tools

UPF flow

Job description

Amazon Leo is seeking a Sr. Physical Design Engineer to drive architectural feasibility and physical implementation for SOCs used in satellite communications. You will collaborate with RTL/Arch teams, optimize power, area, and performance, and guide P&R closure across multi-site teams.

The role emphasizes strong experience in ASIC implementation, UPF flows for low power design, and integration of RF/Analog/Mixed-signal blocks with digital top flows. A Master's and 10+ years are preferred.