SoC Verification Engineer - Testbench Automation Lead

TetraMem - Accelerate The World; San Jose (CA); On-site; USD 110,000 - 300,000; Full time

Job summary

TetraMem - Accelerate The World is seeking an experienced Senior Verification Engineer to define test plans for SoC verification and to build automation infrastructure for architecture, function and performance validation.

You will develop reusable testbenches, constrained-random/test-case strategies and regression tooling while debugging RTL/post-P&R issues and mentoring junior engineers in a startup setting.

Qualifications

• MS with 8+ years of relevant experience or PhD with 3+ years in Electrical/Computer Engineering or related field.
• In-depth knowledge of UVM/OVM, semiformal verification, assertion-based verification and hardware-software co-verification.
• Extensive experience building verification infrastructure, test planning, coverage closure, testbench and test cases for function/performance verification.
• Proficient with Verilog, SystemVerilog, Python/Perl/TCL/Shell scripting, C/C++, SystemC and mainstream ISAs assembly coding.
• Familiarity with MIPI, AMBA bus protocols (APB/AHB/AXI), and RISC-V/ARM or DSP cores.
• Experience verifying RTL and post-P&R gate-level designs.
• Ability to work in a startup environment, independently and as a team lead.

Responsibilities

• Collaborate with design engineers to define, document and implement detailed test plans for SoC verification.
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance.
• Develop reusable testbenches and constrained-random/directed test cases; create verification behavioral modules.
• Develop regression strategies, tooling and scripts; define function coverage and close verification holes.
• Debug and identify root causes of simulation failures with design engineers.
• Support test engineers for post-silicon validation.
• Mentor and coach junior engineers; drive verification efficiency.

Skills

UVM/OVM

Semiformal Verification

Assertion-based verification

Hardware-software co-verification

Verilog

SystemVerilog

Python

Perl

TCL

Shell scripting

C/C++

SystemC

ISA assembly coding

MIPI

AMBA/AXI/APB

RISC-V/ARM/DSP core

Education

MS with 8+ years experience

PhD with 3+ years experience

Tools

Verilog

SystemVerilog

Python

Perl

TCL

Shell scripting

C/C++

SystemC

ISA assembly

Job description

TetraMem - Accelerate The World is seeking an experienced Senior Verification Engineer to define test plans for SoC verification and to build automation infrastructure for architecture, function and performance validation.

You will develop reusable testbenches, constrained-random/test-case strategies and regression tooling while debugging RTL/post-P&R issues and mentoring junior engineers in a startup setting.