ASIC/SoC Design Verification Engineer

TetraMem - Accelerate The World; San Jose (CA); On-site; USD 110,000 - 300,000; Full time

Job summary

TetraMem - Accelerate The World is seeking an experienced Senior Verification Engineer to define test plans for SoC verification and to build automation infrastructure for architecture, function and performance validation.

You will develop reusable testbenches, constrained-random/test-case strategies and regression tooling while debugging RTL/post-P&R issues and mentoring junior engineers in a startup setting.

Qualifications

• MS with 8+ years of relevant experience or PhD with 3+ years in Electrical/Computer Engineering or related field.
• In-depth knowledge of UVM/OVM, semiformal verification, assertion-based verification and hardware-software co-verification.
• Extensive experience building verification infrastructure, test planning, coverage closure, testbench and test cases for function/performance verification.
• Proficient with Verilog, SystemVerilog, Python/Perl/TCL/Shell scripting, C/C++, SystemC and mainstream ISAs assembly coding.
• Familiarity with MIPI, AMBA bus protocols (APB/AHB/AXI), and RISC-V/ARM or DSP cores.
• Experience verifying RTL and post-P&R gate-level designs.
• Ability to work in a startup environment, independently and as a team lead.

Responsibilities

• Collaborate with design engineers to define, document and implement detailed test plans for SoC verification.
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance.
• Develop reusable testbenches and constrained-random/directed test cases; create verification behavioral modules.
• Develop regression strategies, tooling and scripts; define function coverage and close verification holes.
• Debug and identify root causes of simulation failures with design engineers.
• Support test engineers for post-silicon validation.
• Mentor and coach junior engineers; drive verification efficiency.

Skills

UVM/OVM

Semiformal Verification

Assertion-based verification

Hardware-software co-verification

Verilog

SystemVerilog

Python

Perl

TCL

Shell scripting

C/C++

SystemC

ISA assembly coding

MIPI

AMBA/AXI/APB

RISC-V/ARM/DSP core

Education

MS with 8+ years experience

PhD with 3+ years experience

Tools

Verilog

SystemVerilog

Python

Perl

TCL

Shell scripting

C/C++

SystemC

ISA assembly

Job description

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
• Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral module for both of block levels and system levels
• Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
• Work with design engineers to debug and identify root causes of simulation failure
• Support test engineers for post-silicon validation
• Mentor and coach team members and junior engineers. Drive verification efficiency

Responsibilities

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
• Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral module for both of block levels and system levels
• Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
• Work with design engineers to debug and identify root causes of simulation failure
• Support test engineers for post-silicon validation
• Mentor and coach team members and junior engineers. Drive verification efficiency

Requirements

• MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree
• In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology
• Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification
• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core
• Experience in verifying designs at both of RTL level and post-P&R gate level
• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
• Experience in verifying mix-signal design and interface of digital and analog
• Experience of design verification for highspeed IO such as PCIE and DDR

Salary Range:

$110,000 - $300,000 / year

TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.

TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.

To ensure a fair, consistent, and efficient hiring process, all candidates must apply through TetraMem’s official ClearCompany Applicant Tracking System (ATS). Applications submitted through the ATS allow our hiring team to evaluate candidates using a standardized process and ensure timely communication throughout the recruitment process. To promote equal consideration for all applicants, applications submitted outside of the ClearCompany ATS, including direct emails, LinkedIn messages, or unsolicited submissions to employees, may not be reviewed or considered.

We encourage all interested candidates to apply through the official TetraMem Careers page.