Remote Senior ASIC/SoC Verification Engineer

EPITEC; El Segundo (CA); Remote; USD 227,000 - 264,000; Full time

Benefits offered by this job

80 hours paid time off

Medical insurance contributions

401k retirement savings plan

Job summary

EPITEC is seeking a Senior ASIC/SoC Verification Engineer to lead verification strategy and build end-to-end testbenches for a next-generation silicon program. You will own the verification plan, create reusable testbenches, and drive coverage closure from planning to sign-off.

You will work on complex digital blocks, coordinate with designers, and mentor junior engineers while contributing to CI workflows and advanced verification techniques in a fast-paced satellite-domain project.

Qualifications

• 7+ years of ASIC/SoC/RTL/complex digital verification experience preferred.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience developing or contributing to verification environments and testbenches.
• Strong understanding of verification planning and metric-driven verification.
• Experience with Functional coverage, Assertions, Coverage closure, Regression testing, RTL and waveform debugging.

Responsibilities

• Own ASIC/SoC verification activities from test planning through sign-off.
• Build SystemVerilog/UVM testbenches and verification environments from scratch.
• Translate design specs into verification strategies, test plans, and coverage goals.
• Develop verification components including scoreboards, monitors, assertions, coverage models, and reference models.
• Perform constrained-random, directed, formal, and system-level verification.
• Debug RTL, datapath, control logic, testbench, and system-level failures.
• Drive coverage closure, regression health, and verification sign-off.
• Support CI workflows and reusable verification infrastructure across IP and SoC levels.
• Review verification architectures and mentor less-experienced engineers.

Skills

SystemVerilog

UVM

Testbench development

Verification planning

Coverage metrics

Debugging

CI workflows

C/C++ verification

Education

Bachelor's degree in Electrical/Computer Engineering

Job description

EPITEC is seeking a Senior ASIC/SoC Verification Engineer to lead verification strategy and build end-to-end testbenches for a next-generation silicon program. You will own the verification plan, create reusable testbenches, and drive coverage closure from planning to sign-off.

You will work on complex digital blocks, coordinate with designers, and mentor junior engineers while contributing to CI workflows and advanced verification techniques in a fast-paced satellite-domain project.