Senior Analog & Mixed-Signal Design Engineer

TETRAMEM INC; San Jose (CA); On-site; USD 110,000 - 300,000; Full time

Job summary

TetraMem invites engineers to advance analog/mixed-signal verification for cutting-edge memory ICs in a fast-paced setting. You will craft verification plans, build testbenches, and verify circuit behavior end-to-end, collaborating closely with circuit designers.

The role emphasizes strong modeling skills in SystemVerilog, SPICE, and HDL simulations, with opportunities to influence design methodologies and improve verification workflows. Expect a collaborative team and challenging projects.

Qualifications

• Experience in analog and mixed-signal circuit design and verification.
• Ability to write test plans, present results, and communicate with multi-functional teams.
• Familiarity with verification methodologies and tools: simulators, waveform viewers, and coverage.

Responsibilities

• Develop and implement mixed-signal verification and coverage plans for complex IC designs.
• Design and develop verification testbenches using industry-standard methodologies.
• Write and execute test cases to verify mixed-signal circuits for functionality and reliability.
• Review results and provide feedback to design teams.
• Collaborate with design and layout teams to resolve issues.
• Sign-off mixed-signal designs in preparation for tapeout.
• Write SystemVerilog behavioral models for analog/mixed-signal circuits.

Skills

Analog and mixed-signal design

Verification planning

SystemVerilog / Verilog

Python scripting

Team collaboration

Education

Bachelor's degree in Electrical Engineering

Tools

Verilog/SystemVerilog

SPICE simulation

HDL simulation

Job description

TetraMem invites engineers to advance analog/mixed-signal verification for cutting-edge memory ICs in a fast-paced setting. You will craft verification plans, build testbenches, and verify circuit behavior end-to-end, collaborating closely with circuit designers.

The role emphasizes strong modeling skills in SystemVerilog, SPICE, and HDL simulations, with opportunities to influence design methodologies and improve verification workflows. Expect a collaborative team and challenging projects.