ASIC/SoC Design Verification Engineer

TetraMem INC; Fremont (CA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical benefits

Professional PTO

401k plan

Job summary

TetraMem INC is a fast-growing startup based in Fremont, California, seeking an engineer to lead SoC design verification for groundbreaking computing technology. The ideal candidate will collaborate with design engineers, mentor team members, and possess extensive knowledge in verification methodologies like UVM/OVM.

Offering competitive compensation and a complete benefits package, TetraMem is committed to confidentiality and EEO guidelines. Join our innovative team and contribute significantly to the future of computing!

Qualifications

• 8+ years experience in electrical or computer engineering or a related field.
• Expertise in UVM/OVM and assertion-based verification.
• Familiarity with AI/ML Computing and high-speed IO design verification preferred.

Responsibilities

• Collaborate with engineers to implement detailed test plans.
• Build and maintain automation verification infrastructure.
• Develop and measure function coverage strategies.
• Mentor team members and drive verification efficiency.

Skills

UVM/OVM knowledge

Verification infrastructure

Verilog

System Verilog

Python/Perl/TCL/Shell scripting

C/C++

System C

Education

MS in Electrical Engineering, Computer Engineering, Computer Science or related degree with 8+ years

PhD with 3+ years of experience

Job description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.

Job Description

Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification.

Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance.

Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels.

Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out.

Work with design engineers to debug and identify root causes of simulation failure.

Support test engineers for post-silicon validation.

Mentor and coach team members and junior engineers. Drive verification efficiency.

Qualifications

MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree.

In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology.

Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification.

Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding.

Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core.

Experience in verifying designs at both of RTL level and post-P&R gate level.

Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
• Experience in verifying mix-signal design and interface of digital and analog.
• Experience of design verification for high speed IO such as PCIE and DDR.

Additional Information

All your information will be kept confidential according to EEO guidelines.