Static Timing Analysis (STA) Engineer

Oho Group; San Jose (CA); On-site; USD 190,000 - 230,000; Full time

Job summary

Oho Group is seeking an experienced Static Timing Analysis Engineer to lead end-to-end STA and timing signoff for cutting-edge ASIC/SoC designs in a stealth semiconductor startup.

You will develop SDC constraints, debug timing violations, and collaborate with RTL, synthesis, and physical design teams to optimize timing, power, and area while advancing STA methodologies and automation.

Qualifications

• 10+ years' experience in STA and timing signoff for complex ASIC/SoC designs.
• Expert knowledge of Synopsys PrimeTime and Cadence Tempus.
• Strong experience with SDC development, MCMM analysis, OCV/AOCV/POCV, and advanced-node timing closure (7nm/5nm or below).
• Familiarity with Design Compiler and Cadence Genus, SI-aware STA, UPF/CPF, and Tcl scripting.
• Strong analytical skills with the ability to solve complex timing challenges independently.

Responsibilities

• Own end-to-end STA and timing signoff for advanced-node ASIC/SoC designs from synthesis through tapeout.
• Develop and maintain SDC constraints, debug timing violations, and implement timing ECOs.
• Partner closely with RTL, synthesis, and physical design teams to optimise timing, power, and area.
• Enhance STA methodologies, automation, and signoff flows.

Skills

STA timing signoff

PrimeTime

Tempus

SDC development

OCV/AOCV/POCV

Tcl scripting

Genus

Design Compiler

7nm/5nm timing

Tools

Cadence Genus

Job description

A well-funded stealth semiconductor startup building next-generation silicon with an experienced leadership team and ambitious roadmap.

As they grow their engineering organisation, we're looking for an experienced Static Timing Analysis Engineer to play a key role in delivering silicon success.

What You’ll Do

• Own end-to-end STA and timing signoff for advanced-node ASIC/SoC designs from synthesis through tapeout.
• Develop and maintain SDC constraints, debug timing violations, and implement timing ECOs.
• Partner closely with RTL, synthesis, and physical design teams to optimise timing, power, and area.
• Enhance STA methodologies, automation, and signoff flows.

What We’re Looking For

• 10+ years' experience in STA and timing signoff for complex ASIC/SoC designs.
• Expert knowledge of Synopsys PrimeTime and/or Cadence Tempus.
• Strong experience with SDC development, MCMM analysis, OCV/AOCV/POCV, and advanced-node timing closure (7nm/5nm or below).
• Familiarity with Design Compiler and/or Cadence Genus, SI-aware STA, UPF/CPF, and Tcl scripting.
• Strong analytical skills with the ability to solve complex timing challenges independently.