Senior SoC STA Engineer

Innophaseiot; San Diego (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

Innophaseiot in San Diego, California is seeking a highly experienced Senior SoC STA Engineer to own chip-level timing sign-off for next-gen SoC designs. This senior technical role focuses on static timing analysis and timing closure, working closely with cross-functional teams to ensure timing integrity.

The ideal candidate should have over 10 years of hands-on experience with STA, strong programming skills in Python and Tcl, and expertise in using industry-standard tools like Cadence Tempus.

Qualifications

• 10+ years of experience in chip-level STA ownership and full timing sign-off.
• Deep expertise with industry-standard STA tools.
• Strong understanding of advanced timing concepts.

Responsibilities

• Own end-to-end chip-level static timing analysis.
• Drive timing closure through critical path analysis.
• Define and enhance STA methodologies and standards.

Skills

Chip-level STA ownership

Signal integrity

Cross-functional collaboration

Python scripting

Tcl scripting

Education

Bachelor’s degree in Electrical Engineering

Master’s degree (preferred)

Tools

Cadence Tempus

Job description

Job Summary

We are seeking a highly experienced Senior SoC STA Engineer to own chip-level timing sign-off for next-generation SoC designs. In this role, you will work closely with RTL Design, Physical Design, Architecture, DFT, Verification, Product Engineering, and EDA vendors to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape‑out.

This is a hands‑on senior technical role focused on chip-level static timing analysis (STA), timing closure, constraint development, methodology enhancement, automation, and pre‑/post‑silicon timing correlation.

Key Responsibilities

• Own end‑to‑end chip‑level static timing analysis and sign‑off across all checks, modes, process corners, voltage, and temperature conditions.
• Develop, maintain, and validate sign‑off‑quality SDC constraints for clocks, resets, high‑speed I/O interfaces, DFT, and configuration logic.
• Drive timing closure at both block and full‑chip levels through critical path analysis, ECO implementation, and close collaboration with Physical Design teams on floorplanning, placement, CTS, routing, and optimization.
• Perform advanced multi‑mode multi‑corner (MMMC) timing analysis including clock‑domain crossing timing, OCV/AOCV/POCV methodologies, and advanced‑node timing sign‑off.
• Lead signal integrity and crosstalk analysis, identify noise‑induced timing issues, and drive mitigation strategies with implementation teams.
• Conduct pre‑ and post‑silicon timing correlation and drive timing sign‑off readiness reviews and tape‑out closure activities.
• Define and enhance organization‑wide STA methodologies, sign‑off standards, timing closure best practices, and automation infrastructure.
• Build and maintain STA automation and reporting flows using Python and Tcl for regression tracking, QoR analysis, dashboards, and sign‑off reporting.
• Work closely with RTL and System Design teams during early design phases to improve physical awareness and timing convergence.
• Collaborate with cross‑functional teams including RTL Design, Physical Design, Verification, DFT, Product Engineering, and Test Engineering to ensure timing requirements are met throughout the design cycle.
• Drive design and flow improvements, resolve implementation and methodology issues, and execute timing‑related ECOs.
• Develop and improve physical design and timing methodologies to achieve QoR targets for performance, power, and area.
• Interface with EDA vendors to drive tool improvements, evaluate new tool capabilities, and improve design flows and productivity.
• Mentor junior engineers and contribute to technical documentation, sign‑off methodologies, and engineering best practices.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline (Master’s degree preferred).
• 10+ years of hands‑on experience in chip‑level STA ownership and full timing sign‑off across multiple successful tape‑outs at 22nm technology nodes or below.
• Deep expertise with industry‑standard STA tools such as Cadence Tempus.
• Strong understanding of advanced timing concepts including MMMC analysis, OCV/AOCV/POCV, signal integrity, crosstalk, and power‑aware timing methodologies.
• Proven experience developing and managing complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
• Solid understanding of Logic Synthesis and Physical Design methodologies.
• Experience with floorplanning, power planning, CTS specification, place‑and‑route, and timing closure.
• Familiarity with CPF/UPF power intent design and implementation.
• Strong scripting and automation skills using Python and/or Tcl.
• Familiarity with foundry PDKs, Liberty timing models, and advanced variation/noise modeling techniques.
• Experience with DFT timing analysis including scan, MBIST, and JTAG interfaces.
• Strong communication and collaboration skills with the ability to work effectively across cross‑functional teams, IP providers, and EDA vendors.