SoC RTL & Microarchitecture Design Engineer

Jobtailor; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking an experienced SoC design engineer to develop RTL logic, verify microarchitecture, and integrate IP blocks into full-chip designs. You will collaborate with architects to define features, optimize for power and timing, and ensure secure, robust IP-SoC handoffs.

The role emphasizes RTL development, SystemVerilog expertise, and deep understanding of SoC design methodologies, including timing convergence and physical implementation.

Qualifications

• Bachelor's or higher in Electrical/Computer Engineering with 4+ years of experience.
• Master's with 3+ years of relevant work, or PhD with at least 6 months', experience.
• Expertise in RTL, SystemVerilog, and SoC integration practices.
• Strong grasp of microarchitecture, timing, and power-aware design.
• Familiarity with physical implementation workflows.

Responsibilities

• Develop high-quality RTL logic designs and perform simulations for SoCs.
• Collaborate with architects to define microarchitecture features.
• Integrate IP blocks and subsystems into full-chip designs.
• Perform quality checks and optimize for power, performance, and area.
• Review verification plans to ensure design features are verified.
• Apply secure development practices to mitigate risks.
• Collaborate with IP providers for IP integration at the SoC level.
• Support IP-SoC handoffs with QA and documentation.

Skills

RTL development

System Verilog

SoC integration

Microarchitecture definition

Logic design

Simulation

Timing convergence

Power convergence

Physical implementation

Education

Bachelor's degree + 4+ years

Master's degree + 3+ years

PhD + 6+ months experience

Job description

Jobtailor is seeking an experienced SoC design engineer to develop RTL logic, verify microarchitecture, and integrate IP blocks into full-chip designs. You will collaborate with architects to define features, optimize for power and timing, and ensure secure, robust IP-SoC handoffs.

The role emphasizes RTL development, SystemVerilog expertise, and deep understanding of SoC design methodologies, including timing convergence and physical implementation.