SoC Logic Design Engineer

Jobtailor; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking an experienced SoC design engineer to develop RTL logic, verify microarchitecture, and integrate IP blocks into full-chip designs. You will collaborate with architects to define features, optimize for power and timing, and ensure secure, robust IP-SoC handoffs.

The role emphasizes RTL development, SystemVerilog expertise, and deep understanding of SoC design methodologies, including timing convergence and physical implementation.

Qualifications

• Bachelor's or higher in Electrical/Computer Engineering with 4+ years of experience.
• Master's with 3+ years of relevant work, or PhD with at least 6 months', experience.
• Expertise in RTL, SystemVerilog, and SoC integration practices.
• Strong grasp of microarchitecture, timing, and power-aware design.
• Familiarity with physical implementation workflows.

Responsibilities

• Develop high-quality RTL logic designs and perform simulations for SoCs.
• Collaborate with architects to define microarchitecture features.
• Integrate IP blocks and subsystems into full-chip designs.
• Perform quality checks and optimize for power, performance, and area.
• Review verification plans to ensure design features are verified.
• Apply secure development practices to mitigate risks.
• Collaborate with IP providers for IP integration at the SoC level.
• Support IP-SoC handoffs with QA and documentation.

Skills

RTL development

System Verilog

SoC integration

Microarchitecture definition

Logic design

Simulation

Timing convergence

Power convergence

Physical implementation

Education

Bachelor's degree + 4+ years

Master's degree + 3+ years

PhD + 6+ months experience

Job description

Responsibilities

• Develop high-quality logic designs, including Register Transfer Level (RTL) coding and simulations, for innovative SoCs
• Collaborate with architects to define and implement microarchitecture features of SoC blocks
• Integrate and validate Intellectual Property (IP) blocks and subsystems into full-chip SoC designs
• Perform quality checks and optimize designs to meet power, performance, area, and timing objectives
• Review verification plans to confirm design features are thoroughly verified
• Employ secure development practices to mitigate security risks
• Work with IP providers to integrate and validate IPs at the SoC level
• Drive quality assurance compliance to enable efficient IP-SoC handoffs

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of relevant experience
• OR Master's degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of relevant experience
• OR PhD in Electrical Engineering, Computer Engineering, or a related field and 6+ months of experience
• Expertise in RTL development, System Verilog, and SoC logic integration
• Proficiency in microarchitecture definition, logic design, and simulation
• Strong understanding of SoC design methodologies, including timing/power convergence and physical implementation