Sr. Microarchitect & RTL Design Engineer

International Association of Plumbing and Mechanical Officials (IAPMO); Santa Clara, Northern (CA, KY); On-site; USD 180,000 - 240,000; Full time

Job summary

IAPMO in Santa Clara, CA is seeking a seasoned Microarchitect and RTL Design Engineer to shape our IP portfolio, focusing on microarchitecture and RTL coding. You will design configurable IPs and work with hardware, software, and verification teams to deliver high-quality IPs.

Join a team tackling high-speed, pipelined designs with power/area optimization and tight integration with NOc/Caches. Strong RTL capability and collaboration are essential.

Qualifications

• Bachelor's or master's in electrical/computer engineering or computer science.
• 8+ years in microarchitecture and RTL development with hands-on experience.
• Proficiency in Verilog and SystemVerilog with exposure to EDA toolchains.

Responsibilities

• Design and develop microarchitectures for configurable IPs.
• Code RTL with focus on performance, power, and area.
• Collaborate with software for configuration requirements and verifications.
• Work with verification teams on assertions, plans, and coverage.

Skills

Verilog

SystemVerilog

NoCs

Caches & memory subsystems

ARM ACE/CHI coherency

Python

Communication skills

Education

BS or MS in Electrical/Computer Engineering or Computer Science

Tools

EDA tools

Python scripts

Job description

Job Title: Microarchitect & RTL Design Engineer

Location: Santa Clara, CA

About the Role:

We are seeking a seasoned Microarchitect and RTL Design Engineers with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Key Responsibilities:

• Design and develop microarchitectures for a set of highly configurable IPs
• Microarchitecture and RTL coding ensuring optimal performance, power, area
• Collaborate with software teams to define configuration requirements, verification collaterals etc.
• Work with verification teams on assertions, test plans, debug, coverage etc.

Qualifications:

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in microarchitecture and RTL development
• Proficiency in Verilog, System Verilog
• Familiarity with industry-standard EDA tools and methodologies
• Experience with large high-speed, pipelined, stateful designs, and low power designs
• In-depth understanding of on-chip interconnects and NoCs
• Experience within ARM ACE/CHI or similar coherency protocols
• Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NOCs
• Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
• Experience with modern programming languages like Python is a plus
• Excellent problem-solving skills and attention to detail
• Strong communication and collaboration skills