RTL Design Engineer - AI-SoC & IP Integration

Jobtailor; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking an experienced RTL design engineer to contribute to ASIC/SoC development. You will design RTL in Verilog/SystemVerilog, integrate IP blocks, and participate in architectural decisions while ensuring timing, power, and security practices are observed.

You will collaborate with verification teams, perform quality checks from RTL through timing convergence, and apply scripting for automation. This role emphasizes design integrity and efficient integration of CPU subsystems.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 4+ years of RTL design and implementation for ASIC/SoC development.
• Proficiency in Verilog/SystemVerilog for RTL coding and design.
• Experience with synthesis tools and timing closure methodologies.
• Understanding of clock domain crossings, power optimization, and timing closure.
• Exposure to SoC system integration and CPU subsystem design.
• Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
• Knowledge of high-speed and low-power design techniques.
• Experience with static timing analysis (STA) tools and methodologies.
• Hands-on experience with formal verification tools and techniques.
• Basic scripting skills (Python, TCL, etc.) for automation.

Responsibilities

• develop logic design, register transfer level (RTL) coding, and simulation for SoC designs
• integrate IP blocks and subsystems into full chip SoC or discrete component designs
• participate in defining architecture and microarchitecture features
• perform quality checks across various logic design aspects from RTL to timing/power convergence
• apply strategies, tools, and methods to write RTL and optimize logic
• ensure design integrity for physical implementation
• work closely with verification teams, review verification plans and resolve failing RTL tests
• follow secure development practices and collaborate with IP providers

Skills

RTL design

Verilog/SystemVerilog

Synthesis tools

Timing closure

Clock domain crossings

SoC integration

Embedded CPU architectures

High-speed & low-power design

STA tools

Formal verification

Python scripting

TCL scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Synthesis tools

STA tools

Formal verification tools

Job description

Jobtailor is seeking an experienced RTL design engineer to contribute to ASIC/SoC development. You will design RTL in Verilog/SystemVerilog, integrate IP blocks, and participate in architectural decisions while ensuring timing, power, and security practices are observed.

You will collaborate with verification teams, perform quality checks from RTL through timing convergence, and apply scripting for automation. This role emphasizes design integrity and efficient integration of CPU subsystems.