SoC RTL Integration Lead — Full-Chip, Hybrid

NVIDIA; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA is seeking a Full-Chip RTL Integration Engineer to join the Advanced Technology Group. You will lead RTL integration of IPs into complex ASIC/SoC designs, drive system-level integration, and ensure design closure.

Apply your SystemVerilog/UVM experience, DFT knowledge, and scripting skills to improve automation and debugging, while collaborating across Architecture, Verification, and Physical Design teams.

Qualifications

• B.S. or M.S. in Electrical/Computer Engineering with 8+ years of experience.
• Experience in ASIC/SoC RTL Integration.
• Understanding of digital design fundamentals, SoC architecture, clocking, reset, and bus protocols.
• Strong verification knowledge with SystemVerilog and UVM.
• Ability to independently verify block- and integration-level designs.
• DFT methodologies including Scan, ATPG, MBIST, LBIST, JTAG, and test compression.

Responsibilities

• Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration.
• Work closely with Architecture, RTL Design, Verification, DFT, and Physical Design teams to drive system-level integration and design closure.
• Perform RTL quality checks including lint, CDC, RDC, synthesis, and connectivity validation.
• Develop and carry out integration-level verification plans using SystemVerilog/UVM, debug simulation failures, and support functional coverage closure.
• Collaborate with DFT teams to integrate scan, MBIST, LBIST, JTAG, and other test structures, and review ATPG reports and fault coverage metrics to ensure testability requirements are met.
• Support design signoff activities and ensure smooth handoff across implementation stages.
• Develop automation and scripting solutions to improve integration, verification, and debug productivity.

Skills

RTL Integration

SystemVerilog/UVM

ASIC/SoC

DFT Methods

Lint CDC RDC

Debugging

Scripting

Cross-Functional

Education

B.S. or M.S. in EE/CE

Tools

Synopsys

Cadence

Siemens DFT

Job description

NVIDIA is seeking a Full-Chip RTL Integration Engineer to join the Advanced Technology Group. You will lead RTL integration of IPs into complex ASIC/SoC designs, drive system-level integration, and ensure design closure.

Apply your SystemVerilog/UVM experience, DFT knowledge, and scripting skills to improve automation and debugging, while collaborating across Architecture, Verification, and Physical Design teams.