SOC RTL Integration Architect

MatX; Mountain View (CA); Hybrid; USD 160,000 - 275,000; Full time

Benefits offered by this job

4 weeks PTO

12 company holidays

Up to 3 weeks remote work

Medical, dental, vision

401K with company match

Professional development budget

Team meals

Commute support

Remote home setup stipend

Job summary

MatX is seeking silicon micro-architects and design engineers to deliver high-performance, scalable SOC RTL for the next generation of GenAI workloads. The role focuses on architecture-to-design methodology, top-level RTL, and automated flows to enable on-the-fly SOC integration.

You will collaborate across design, physical design, and system teams to ensure floorplan-connected RTL, robust clock/reset, and timing constraints while supporting packaging and board teams with SOC pin definitions.

Qualifications

• Proficiency in SystemVerilog and scripting languages.
• Experience integrating CPUs/GPUs/accelerators and high-speed interconnects.
• Knowledge of SOC-level verification and floorplanning considerations.
• Experience with DV flows for SOC RTL.

Responsibilities

• Drive the evolution of silicon architecture-to-design methodology for full-chip SOC RTL.
• Partner with SubSystem owners to integrate blocks and develop SOC Top-level RTL.
• Implement automation for SOC top-level RTL integration and build processes.
• Collaborate with Physical Design to incorporate RTL modules and floorplan connectivity.
• Establish clock and reset methodologies across teams.
• Define and support SoC timing constraints and validate against designs.
• Provide tech support to packaging/board teams by defining SOC pin requirements.

Skills

SystemVerilog

Python

Perl

SoC integration

UCIE interconnect

Memory management

Verification (SOC)

DFT wrappers

RTL design

Design automation

Synthesis timing

Emulation

Tools

Synthesis tools

Linting tools

Clock domain crossing

DV flows

Job description

MatX is seeking silicon micro-architects and design engineers to deliver high-performance, scalable SOC RTL for the next generation of GenAI workloads. The role focuses on architecture-to-design methodology, top-level RTL, and automated flows to enable on-the-fly SOC integration.

You will collaborate across design, physical design, and system teams to ensure floorplan-connected RTL, robust clock/reset, and timing constraints while supporting packaging and board teams with SOC pin definitions.