Senior RTL & FPGA Integration Engineer

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose seeks a Senior FPGA/RTL design engineer to drive high-performance silicon, leveraging RTL design methodologies, AI-assisted automation, and modern EDA tools. You will collaborate across time zones with architects, HW and SW teams to deliver next-gen FPGA products.

The role emphasizes cross-functional execution, verification, and timely delivery of IP features, with a focus on PPA optimization and integration within the AECG group.

Qualifications

• Bachelor’s or Master’s in Computer Engineering or Electrical Engineering.
• RTL design (Verilog/SystemVerilog) and digital/analog block implementation.
• Understanding of VLSI design flow from RTL through Physical Design and GDSII.
• Familiarity with Physical Implementation: floorplanning, synthesis, P&R, STA.
• Experience with EDA tools: Design Compiler, Primetime, VCS, Cadence Virtuoso.
• Knowledge of UVM/OVM verification, simulation environments, debugging.

Responsibilities

• Collaborate with architects, hardware and SW-FW engineers to define product requirements and IP features.
• Build early-stage RTL designs based on product intent guiding Silicon and Solution co-development.
• Build and enhance AI-driven infrastructure to accelerate IP integration and timelines.
• Apply data-driven methods to align engineering across next-gen products and nodes.
• Support functional simulation and software quality checks with robust verification coverage.
• Partner with global teams to ensure seamless integration and delivery.

Skills

RTL design

Verilog/SystemVerilog

VLSI flow

EDA tools

UVM/OVM

FPGA arch

Scripting

Education

Bachelor’s or Master’s in Computer or Electrical Engineering

Tools

Synopsys Design Compiler

Primetime

VCS

Cadence Virtuoso

Job description

Advanced Micro Devices, Inc. in San Jose seeks a Senior FPGA/RTL design engineer to drive high-performance silicon, leveraging RTL design methodologies, AI-assisted automation, and modern EDA tools. You will collaborate across time zones with architects, HW and SW teams to deliver next-gen FPGA products.

The role emphasizes cross-functional execution, verification, and timely delivery of IP features, with a focus on PPA optimization and integration within the AECG group.