SoC Power Modeling Engineer – Optimize AI/ML & IPs

Apple Inc.; Cupertino (CA); On-site; USD 142,000 - 263,000; Full time

Benefits offered by this job

Medical coverage

Dental coverage

Stock programs

RSU awards

Education reimbursement

Relocation assistance

Job summary

Apple Inc. in Cupertino is seeking an ASIC power modeling engineer to design and validate power delivery and DVFM points for IPs and SOCs. You will model and optimize power behavior across multiple Apple silicon blocks to support energy-efficient products.

You will collaborate with architecture, design, thermals, PMIC and lab teams to correlate models with hardware data, enabling accurate power predictions and robust silicon performance.

Qualifications

• Bachelor's degree in a relevant field with at least 3 years of industry experience.
• Strong programming and data analysis skills; experience with low-power digital design.
• Understanding of SOC power modeling, PDN, power gating and power delivery.
• Familiarity with physical design tools for power optimization.

Responsibilities

• Model power dissipation and power delivery for IPs and SOC.
• Establish voltage points for DVFM states across IPs.
• Collaborate with architecture, design, thermals, PMIC and lab teams to align models with HW data.
• Assist with silicon validation and lab correlation.

Skills

Programming skills

Data analysis

Low-power design

VLSI design

Education

Bachelor's degree in EE/CS

Tools

EDA tools

Job description

Apple Inc. in Cupertino is seeking an ASIC power modeling engineer to design and validate power delivery and DVFM points for IPs and SOCs. You will model and optimize power behavior across multiple Apple silicon blocks to support energy-efficient products.

You will collaborate with architecture, design, thermals, PMIC and lab teams to correlate models with hardware data, enabling accurate power predictions and robust silicon performance.