SoC Power Modeling Engineer – AI/ML & Power Optimization

Apple Inc.; Austin (TX); On-site; USD 140,000 - 180,000; Full time

Job summary

Apple is seeking an engineer in the Silicon Engineering group to model power dissipation and DVFS points for SOC IPs, including AI/ML accelerators. You will work with architecture, design, thermals, PMIC and system teams to optimize power profiles and ensure model correlation with hardware data.

The role emphasizes scripting, data analysis, and familiarity with low-power digital design and CMOS technology to drive energy-efficient silicon for Apple products.

Qualifications

• Bachelor's degree in a relevant field and 3+ years of industry experience.
• Experience in ASIC power modeling or DVFS design is preferred.
• Strong scripting and data analysis capabilities are required.

Responsibilities

• Model power dissipation and power delivery for IPs and SOC blocks.
• Establish voltages for DVFM states and operating points pre- and post-silicon.
• Collaborate with architecture, design, thermals, PMIC and system teams.
• Coordinate with lab and silicon validation teams to correlate models with HW data.
• Support optimization of power profiles for AI/ML accelerators and CPUs.

Skills

Programming skills

Low-power design

Power modeling

Scripting

Data analysis

Communication

Education

Bachelor's degree

Tools

EDA tools

Python

CMOS process knowledge

Job description

Apple is seeking an engineer in the Silicon Engineering group to model power dissipation and DVFS points for SOC IPs, including AI/ML accelerators. You will work with architecture, design, thermals, PMIC and system teams to optimize power profiles and ensure model correlation with hardware data.

The role emphasizes scripting, data analysis, and familiarity with low-power digital design and CMOS technology to drive energy-efficient silicon for Apple products.