Member of Technical Staff - Microarchitect / RTL Design

Architect Labs; Palo Alto (CA); On-site; USD 180,000 - 320,000; Full time

Benefits offered by this job

Equity stake

Autonomy with impact

Cutting-edge AI and silicon design

Job summary

Architect Labs is seeking a Senior RTL Design staff member to own the AI-driven RTL design flow for production silicon. You will collaborate with the principal architect to refine microarchitectural specs and ensure area, timing, and power closure while defining robust interface standards for block and SS integration.

You will work across DV, SW, and ML teams to optimize the AI flow and support FPGA prototyping for early validation, with an emphasis on AMBA protocols and on-chip memory and

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• 5+ years (10+ preferred) in RTL design with tapeout experience.
• SystemVerilog: synthesizable, lint-clean RTL with modular design.
• Block-level compute datapaths and data movement experience.
• Solid grasp of AMBA protocols (AXI, AHB, APB) and power management.
• Strong Python skills for design automation and tooling.
• Leadership to guide RTL design efforts and grow into a team lead.

Responsibilities

• Own AI‑driven RTL design flow end-to-end from frontend to lint/CDC/synthesis and timing closure.
• Refine microarchitectural specs with the principal architect and feed back area/time/power constraints.
• Define and maintain interface specifications for block- and SS-level integration.
• Build and maintain RTL infrastructure and regression flows for in-house AI-driven flow.
• Collaborate with DV to bring up reference models and ensure verification closure.
• Collaborate with SW/ML to improve in-house AI flow based on experience.
• Support FPGA prototyping on Xilinx for early functional validation.

Skills

RTL design

SystemVerilog

Block-level depth

SoC methodology

Python

PPA ownership

Leadership

Education

Bachelor's/Master's/PhD in Electrical or Computer Engineering

Job description

Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.

What You'll Do

As a Member of the Technical Staff on the RTL Design team at Architect, you'll own the AI-driven microarchitecture and RTL design of mission-critical SoC blocks and sub-systems (SS) going into production silicon. You will be expected to define, drive, and revise the block-level micro-arch specification for one of the fundamental HW accelerator blocks.

As such, you fit our current opportunities if you have hands-on design and block-owner experience in any of the following ASIC components: on-chip memory SS, on-chip interconnect SS (NoCs, DMAs, etc.) with custom or standard protocols (AXI, etc.), IO and peripherals integration (PCIe, DDR, CXL, etc.), CPU/Host/controllers, Security, Compression, Debug/DFT (BIST, MBIST, etc.), and specialized accelerators such as ML/AI accelerators (NPUs, TPUs, etc.), SIMD vector engines, DSPs, GPUs, graphics/audio pipelines.

As a lab, we are investing in building a world‑class HW design team, so if you think you have a particular experience/background that is not listed here, please still reach out to us!

• Own AI‑driven RTL design flow end-to-end (at the frontend): through code generation to incorporating feedback from lint, CDC, synthesis, and timing closure stages for closing the design loop.
• Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade‑offs, and feed area/timing/power realities back into the architecture and internal AI systems.
• Define and maintain interface specifications (e.g. AXI, AXI-Stream, or custom-built) for block- and SS‑level integration.
• Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral.
• Close collaboration with DV: Support DV bring‑up with reference models, assertions, test‑plans, and architectural documentation for verification closure.
• Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your own experience.
• Support FPGA prototyping on Xilinx for early functional validation.

What We'd Like to See

Qualifications & Skills

• Degree: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience, worked on specialized HW accelerators.
• SystemVerilog: Clear, synthesizable, lint‑clean RTL with strong design habits such as parameterization, modularity, reuse and configurability.
• Block-Level Depth: Hands‑on experience with block-specific compute datapaths and data movement; such as MAC arrays, vector units, accumulators, on‑chip SRAM controllers and arbiters, DMA engines, scratchpad memory management, etc.
• SoC Methodology: Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, AMBA protocols (AXI, AHB, APB), power management techniques, etc.
• Python: Strong skills for design automation, regression infrastructure, and tooling.
• PPA Ownership: Experience taking a block from RTL through synthesis and working with PD teams on timing/area/power closure.
• Leadership: Ability to lead RTL design efforts and grow into a team lead over time.

Bonus

• FPGA prototyping experience (ideally Xilinx Vivado/Vitis).
• Familiarity with SIMD/VLIW execution pipelines or instruction-driven datapath design.
• Experience writing SVA assertions and functional coverage for design-side verification.
• Prior IP building and delivery experience on your block-of-expertise, such as DMA controllers, memory subsystems, interconnects, or similar SoC infrastructure blocks.
• Domain‑specific expertise: Track record on research and development on energy‑efficient, high‑performance HW accelerators on your block-of-expertise.

What We Offer

• Competitive salary and meaningful equity stake
• Fast‑paced startup with autonomy and visible impact
• Cutting‑edge challenges at the intersection of AI and silicon design