SoC Logic Design Engineer - RTL, Power and Security

Intel; Hillsboro (OR); Hybrid; USD 141,910 - 200,340; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel is seeking an experienced SoC Logic Design Engineer in a hybrid role across US locations including Hillsboro, OR. You will develop RTL and logic for SoC blocks, integrate IPs, and contribute to architecture decisions to optimize power, performance, and area.

You will collaborate with cross-functional teams, validate designs, and ensure secure hardware practices, with a focus on meeting timing and physical implementation requirements.

Qualifications

• RTL coding with Verilog and related methodologies.
• Experience in SoC integration, clocking, and low-power design methodologies.
• Proficiency in timing, power convergence, and physical implementation optimization.
• Hands-on experience with Clock Domain Crossing techniques and NoC architectures.
• Familiarity with AMBA protocols CHI, AXI, AHB, and APB.

Responsibilities

• Develop logic designs and RTL code for SoC blocks and subsystems.
• Integrate IP blocks and subsystems into full-chip SoC designs.
• Contribute to architecture/microarchitecture feature definitions.
• Optimize designs to meet power, performance, area, and timing goals.
• Conduct design quality checks and readiness for physical implementation.
• Review verification plans and address RTL test failures.
• Apply secure development practices in hardware design.
• Collaborate with IP providers to validate IPs at the SoC level.
• Ensure QA compliance for IP/SoC handoff.

Skills

RTL coding (Verilog)

SoC integration

Clocking

Low-power design

Timing optimization

Physical implementation

Clock Domain Crossing

NoC architectures

AMBA CHI/AXI/AHB/APB

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in a related field (optional)

Job description

Intel is seeking an experienced SoC Logic Design Engineer in a hybrid role across US locations including Hillsboro, OR. You will develop RTL and logic for SoC blocks, integrate IPs, and contribute to architecture decisions to optimize power, performance, and area.

You will collaborate with cross-functional teams, validate designs, and ensure secure hardware practices, with a focus on meeting timing and physical implementation requirements.