Silicon Logic Design Engineer

VeriFast Technologies; San Jose (CA); Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

Hybrid work arrangement

Job summary

VeriFast Technologies seeks a Sr. Logic Design Engineer with 8+ years of experience to own RTL blocks for memory and high-performance digital IP. Hybrid work option, based in San Jose, CA or Hillsboro, OR.

You will design SystemVerilog/Verilog RTL, evaluate PPA trade-offs, and collaborate with architecture, verification and physical design to meet timing and power goals.

Qualifications

• 8+ years of experience in ASIC/FPGA RTL design.
• Experience with memory controllers and high‑performance interconnects is highly desirable.
• Proficiency in SystemVerilog/Verilog RTL and modern simulation environments.

Responsibilities

• Define micro-architecture and produce production-quality RTL for complex digital logic blocks.
• Evaluate performance, power, and area trade-offs to guide architecture and implementation.
• Collaborate with design verification and physical design teams to ensure timing and success.

Skills

SystemVerilog

Verilog RTL design

ASIC/FPGA logic design

Scripting languages (Python, Perl, Tcl

Education

BSEE or MSEE with 8+ years of ASIC/FPGA RTL experience

Tools

Questa

Xcelium/Incisive

VCS

Job description

Sr. Logic Design Engineer (8+ years experience)

We are seeking an experienced Logic Design Engineer to join a growing semiconductor engineering team developing advanced memory and high-performance digital IP. The position may be based in San Jose, California or Hillsboro, Oregon, with a hybrid working arrangement.

This role is ideal for an accomplished RTL designer who enjoys owning complex blocks from architectural definition through implementation and integration. You will contribute to the development of next-generation memory subsystem technology for demanding applications including data center, high-performance computing, and artificial intelligence.

As an individual contributor, you will work closely with architecture, verification, physical design, applications, and customer-facing engineering teams. The position offers significant technical ownership and the opportunity to influence architecture, performance, and implementation decisions on advanced semiconductor products.

Employees in office-based positions generally work onsite approximately three days per week, with flexibility to work remotely for the remaining days.

Responsibilities

• Define micro-architecture and develop production-quality RTL for complex digital logic blocks.
• Design functionality such as scheduling logic, command and transaction pipelines, ordering/coherency mechanisms, control logic, and high-performance system interfaces.
• Evaluate performance, power, and area (PPA) trade-offs and use quantitative analysis to guide architectural and implementation decisions.
• Partner with design verification engineers to develop verification strategies, identify corner cases, and improve functional coverage.
• Collaborate with physical design engineers to address timing closure, power, utilization, and routing/congestion challenges.
• Investigate regression failures, perform root-cause analysis, and implement RTL corrections when required.
• Participate in design reviews, architecture discussions, and technical problem-solving across engineering disciplines.
• Support customer-facing engineering teams during technical evaluations and pre-sales activities.
• Assist applications and product engineering teams with integration, deployment, and post-delivery technical issues.

Qualifications

• Strong expertise in SystemVerilog and Verilog RTL design.
• Extensive experience developing complex ASIC and/or FPGA logic.
• Experience with industry-standard simulation environments such as Questa, Xcelium/Incisive, or VCS.
• Proficiency with scripting languages such as Python, Perl, and/or Tcl.
• Strong understanding of digital design principles, micro-architecture, timing, and hardware implementation.
• Ability to independently analyze complex technical problems and drive them to resolution.
• Strong written and verbal communication skills and the ability to collaborate effectively across engineering organizations.
• Experience managing technical priorities and delivering designs according to project schedules.

Experience

• BSEE with 10+ years of relevant ASIC/FPGA logic design experience, or
• MSEE with 8+ years of relevant ASIC/FPGA logic design experience.

Experience with memory controllers, high-performance interconnects, cache/coherency architectures, or data-center silicon is highly desirable.