Senior SoC Verification Architect for AI/HPC

TylSemi, Inc.; San Jose (CA); On-site; USD 150,000 - 300,000; Full time

Job summary

TylSemi, Inc. in San Jose, CA is seeking a Design Verification Architect to lead large-scale SoC verification strategies for AI, HPC, and Networking applications.

You will define verification architectures, build reusable testbenches, and drive automation and AI-driven methodologies to accelerate first-pass silicon success while collaborating across design, architecture, and software teams.

Qualifications

• 12+ years in Design Verification for large SoCs.
• Experience deploying verification architectures for complex chips.
• Hands-on with SystemVerilog, UVM, and coverage-driven verification.
• Familiarity with Portable Stimulus (PSS) and cross-level stimulus reuse.

Responsibilities

• Define and drive the overall verification architecture for large-scale SoCs.
• Develop reusable, modular, portable verification platforms across IP to full SoC.
• Establish methods for reuse and portability including PSS-based flows.
• Create high-performance, coverage-driven testbenches (UVM) and sign-off criteria.
• Champion fail-fast verification and first-pass silicon success initiatives.
• Collaborate with design, architecture, PD, and software teams; mentor DV teams.

Skills

SystemVerilog

UVM

Code coverage

Portable Stimulus

AI-driven verification

Debugging hardware

Education

Bachelor's/Master's in EE/CE

Tools

Emulation platforms

Verification frameworks

Job description

TylSemi, Inc. in San Jose, CA is seeking a Design Verification Architect to lead large-scale SoC verification strategies for AI, HPC, and Networking applications.

You will define verification architectures, build reusable testbenches, and drive automation and AI-driven methodologies to accelerate first-pass silicon success while collaborating across design, architecture, and software teams.