Lead SoC DV Architect for Scalable AI Silicon

TylSemi, Inc.; San Jose (CA); Hybrid; USD 238,000 - 286,000; Full time

Benefits offered by this job

Equity stock options

Remote-friendly / Hybrid work

Job summary

TylSemi, Inc. in San Jose, CA is seeking a Lead SoC Design Verification Engineer to drive the verification strategy for next-generation silicon.

You will lead a team of DV engineers, architect modular UVM environments, and ensure first-time silicon quality through constrained-random testing, SVA, and formal methods.

The role rewards deep technical expertise, cross-functional collaboration with Front-End, Emulation, and Post-Silicon teams, and potential equity in a fast-growing AI/ chiplet startup.

Qualifications

• 12+ years hardware verification experience.
• Tape-out on complex, large-scale SoCs.
• Master-level SystemVerilog/UVM expertise.
• Strong cross-functional communication and collaboration.

Responsibilities

• Architect the verification strategy and lead the DV team.
• Translate architectural specs into verification plans and testbenches.
• Develop modular UVM environments and CI-friendly test suites.
• Own sign-off criteria, coverage targets, and regression metrics.
• Collaborate with Front-End, Emulation, and Post-Silicon teams.

Skills

SystemVerilog

UVM

Constrained-random

Functional coverage

SVA

Tape-out experience

Cross-functional communication

Education

Bachelors/Masters in EE/CE/CS

Tools

EDA simulators

Debug platforms

Job description

TylSemi, Inc. in San Jose, CA is seeking a Lead SoC Design Verification Engineer to drive the verification strategy for next-generation silicon.

You will lead a team of DV engineers, architect modular UVM environments, and ensure first-time silicon quality through constrained-random testing, SVA, and formal methods.

The role rewards deep technical expertise, cross-functional collaboration with Front-End, Emulation, and Post-Silicon teams, and potential equity in a fast-growing AI/ chiplet startup.