Senior SoC Verification Engineer — UVM & SystemVerilog

BayOne Solutions; Carlsbad (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

BayOne Solutions is seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create top-tier SoC verification strategies and test environments. You will participate in architectural decisions and verification planning to ensure first-time-right delivery.

Responsibilities include UVM-based environments, block- and system-level plans, and debug leadership. A strong background in SystemVerilog and high-speed interfaces is preferred for influencing silicon

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Experience in UVM-based verification environments and testbench development.
• Proficiency in SystemVerilog and ASIC/SoC verification.
• Experience creating verification plans and debug of complex issues.
• Familiarity with Python or Perl for automation and scripts.
• Knowledge of high-speed protocols (UCIe, PCIe) preferred.

Responsibilities

• Develop and implement UVM-based verification environments.
• Create verification plans at block and system levels.
• Design verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Skills

UVM verification

SystemVerilog

ASIC/SoC verification

Verification test plans

Debug complex issues

C for firmware bringup

Python

Perl

UCIe/PCIe protocols

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Communications Engineering

Tools

SystemVerilog

Python

Perl

Formal verification tools

Job description

BayOne Solutions is seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create top-tier SoC verification strategies and test environments. You will participate in architectural decisions and verification planning to ensure first-time-right delivery.

Responsibilities include UVM-based environments, block- and system-level plans, and debug leadership. A strong background in SystemVerilog and high-speed interfaces is preferred for influencing silicon