SoC Design Verification Engineer

Encore Semi, Inc.; San Jose (CA); Hybrid; USD 100,000 - 150,000; Full time

Job summary

An established industry player is seeking a SoC Design Verification Engineer to join their dynamic team. This role offers the opportunity to work on cutting-edge semiconductor technologies, constructing IP and SoC level test benches while collaborating with architects and designers. With a focus on functional coverage and code coverage, you will utilize your extensive experience in SystemVerilog and UVM to ensure the highest verification standards. If you are passionate about hardware and software co-verification and thrive in a collaborative environment, this is the perfect opportunity to advance your career.

Qualifications

• 10+ years in design verification from test plan development to tape-out sign-off.
• Experience in constructing SystemVerilog and UVM test benches.

Responsibilities

• Construct IP and SoC level test benches using verification components.
• Develop and execute SoC verification plans focused on IP block interoperability.

Skills

SystemVerilog

UVM

Python

Tcl

RTL Debugging

Verification Tools

Education

BSEE

MSEE

Tools

NC Verilog

VCS

QuestaSim

Job description

Join to apply for the SoC Design Verification Engineer role at Encore Semi, Inc..

Location: San Jose, CA or Remote/work from home from any US location.

Full-Time: Salary + Benefits + Bonuses.

Key Responsibilities

1. Construct IP, SoC level test benches using verification components developed at the IP level, including custom and off-the-shelf VIP/UVCs.
2. Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level, based on design specifications and collaboration with architects and designers.
3. Construct HW/SW Co-Verification environments.
4. Participate in a dynamic team with opportunities for modeling (TLM), HW emulation/acceleration, and SW driven verification.
5. Utilize constrained random verification, functional coverage, code coverage, and assertions to meet verification goals.

Job Requirements

1. BSEE required, MSEE preferred or equivalent.
2. 10+ years in design verification, with proven experience from test plan development to tape-out sign-off.
3. Experience constructing chip-level SystemVerilog and UVM test benches, writing SystemVerilog Assertions (SVAs), with embedded software design and testing.
4. Experience executing block or chip-level verification plans.
5. Experience with HW/SW Co-Verification, including developing test benches, test cases, APIs, execution, and debugging.
6. Excellent RTL debugging skills.
7. Extensive experience with verification tools and environments, and understanding their differences to optimize methodology.
8. Proficiency in SystemVerilog, UVM, scripting languages like Python and Tcl.
9. Experience with industry-standard simulation tools such as NC Verilog, VCS, QuestaSim.
10. Excellent communication skills, energetic, and self-motivated.

Additional Information

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Industries: Semiconductor Manufacturing and Computer Hardware Manufacturing