Senior Design Verification Engineer (remote)

Chelsea Search Group, Inc.; Phoenix (AZ); Remote; USD 90,000 - 130,000; Full time

Job summary

An innovative firm is seeking a Senior Design Verification Engineer to join their dynamic team remotely. This role involves developing and executing verification plans for digital designs using SystemVerilog and UVM, alongside collaborating with cross-functional teams to ensure high-quality outputs. You'll be responsible for creating comprehensive testbenches and debugging RTL designs. If you have a passion for cutting-edge technology and thrive in a fast-paced environment, this opportunity is perfect for you. Join a forward-thinking company that values creativity and innovation in the engineering field.

Benefits

Benefits

401k

Stock Options

Qualifications

• 5+ years of experience in SoC verification with UVM.
• Strong background in digital design and ASIC development flow.

Responsibilities

• Develop and execute verification plans for digital designs.
• Run simulations to verify design specifications and debug issues.

Skills

SoC verification using UVM

SystemVerilog

Gate level simulation

Synopsys verification tools (VCS, Verdi, Spyglass)

Digital design concepts

RTL debugging

C/C++/Python/Perl programming

Collaborative teamwork

Multi-tasking in fast-paced environments

Education

BSEE/MSEE

Tools

Git

Job description

Senior Design Verification Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options

Responsibilities:
• Develop and execute verification plans for digital designs using SystemVerilog and UVM
• Create and maintain testbenches, test cases, and test vectors
• Contribute to the development of novel methodologies and verification techniques
• Run simulations to verify design against specifications and analyze results, identify issues, and debug designs
• Implement coverage tracking and metrics
• Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies
• Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.

Required Skills:
• BSEE/MSEE with 5+ years of hands-on experience in SoC verification using UVM
• Experience in gate level simulation setup and process corner failure analysis
• Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass
• Experience with digital design concepts and ASIC development flow
• Experience writing and debugging RTL using SystemVerilog
• Programming experience using C, C++, and/or Python/Perl
• Ability to work collaboratively across teams and communicate effectively
• Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects

Preferred Skills:
• Experience verifying high-speed interfaces such as PCIe and DDR
• Experience verifying RISC-V based systems
• Experience with emulation or FPGA prototyping
• Experience with formal verification methodologies
• Experience with the Chisel hardware description language
• Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines

#SoC #UVM #SystemVerilog #SoCDesign #DesignVerification