SoC Design Verification Engineer

Encore Semi Llc; El Segundo (CA); Remote; USD 90,000 - 140,000; Full time

Job summary

An innovative company is seeking a SoC Design Verification Engineer to join their dynamic team. This role involves developing advanced testbenches and integrating complex systems, ensuring seamless communication between hardware and software components. The ideal candidate will have extensive experience in RTL design and verification, with a strong command of System Verilog UVM. You will collaborate with cross-functional teams to enhance coverage and optimize automated flows. This is an exciting opportunity to work on cutting-edge technology in a supportive and forward-thinking environment, where your contributions will drive significant advancements in the industry.

Qualifications

• 5+ years in RTL Design and Verification, with 2+ years in SoC Design Verification.
• Deep knowledge of System Verilog UVM and testbench integration.

Responsibilities

• Develop testbenches using System Verilog UVM and C.
• Work with cross-functional teams for coverage scope identification.

Skills

System Verilog UVM

C programming

Testbench development

Power Aware simulations

Python Scripting

AHB, AXI, APB protocols

RISC-V and ARM CPU architectures

Tools

Synopsys VCS

Synopsys Verdi

Job description

Job Title: SoC Design Verification Engineer
Locations: Los Angeles, CA or Remote
Full-Time: Salary + Benefits + Bonuses

Responsibilities:
• Testbench development - System Verilog UVM and C tests
• Integration/development of C tests/APIs and SW build flow
• Integration/development of UVM mailboxes and HW/SW communication components
• Integration of lower level UVM testbenches
• Test plan development
• Power Aware testbench development and simulations
• Seamless porting between simulation/emulation/prototyping platforms
• Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
• Coverage collection and closure
• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Minimum Qualifications:
• 5+ years of experience in RTL Design and Verification area of which 2+ years of experience in SoC Design Verification and HW/SW verification
• Deep knowledge of System Verilog UVM and vertical testbench integration
• Knowledge of low level HW/SW interaction and debug
• Knowledge of multi CPU and debug architectures
• Knowledge on AHB, AXI and APB Amba protocols
• Experience with development of fully automated flows

Preferred Qualifications:
• Experience with low level SW debug - disasm, Tarmac, trace
• Experience with RISC-V and ARM CPU architectures
• Experience with CoreSight architecture
• Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
• Experience with coverage merging across simulation and emulation
• Experience with Power Aware and Gate Level Netlist in Emulation
• Experience with development of fully automated flows
• Experience with Gate Level Simulations
• Experience with Synopsys tools VCS & Verdi
• Python Scripting