SoC Design Verification Engineer

Velaura; Austin (TX); On-site; USD 75,000 - 275,000; Full time

Benefits offered by this job

Equity participation

Competitive benefits

Job summary

Velaura in Austin, Texas, seeks Design Verification Engineers to verify its next‑generation Physical AI SoC. You will work with architects, RTL, software and system teams to ensure correctness, performance and safety across the platform.

Responsibilities include developing verification strategies, building environments with SystemVerilog, UVM and C/C++, and driving bug investigation and root-cause analysis across HW/SW boundaries, including emulation and pre‑silicon software bring‑up.

Qualifications

• Experience verifying complex digital systems.
• Strong analytical and problem-solving skills.
• Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals.
• Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.
• Familiarity with formal verification techniques and tools.
• Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.
• Experience debugging complex system-level issues.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Responsibilities

• Develop and execute verification strategies for key portions of the SoC.
• Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.
• Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
• Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
• Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
• Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
• Develop assertions, checkers, scoreboards, and automated verification infrastructure.
• Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
• Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
• Post-silicon debug and root cause analysis.
• Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Skills

SystemVerilog

UVM

C/C++

Digital design fundamentals

SoC architecture

Tools

Assertions

Formal verification

Emulation

Job description

Velaura in Austin, Texas, seeks Design Verification Engineers to verify its next‑generation Physical AI SoC. You will work with architects, RTL, software and system teams to ensure correctness, performance and safety across the platform.

Responsibilities include developing verification strategies, building environments with SystemVerilog, UVM and C/C++, and driving bug investigation and root-cause analysis across HW/SW boundaries, including emulation and pre‑silicon software bring‑up.