CPU Verification Engineer: SystemVerilog & UVM Expert

Intel Corporation; Austin (TX); Hybrid; USD 106,000 - 200,000; Full time

Job summary

Intel Corporation in Austin, Texas, seeks a CPU Design Verification Engineer to ensure functional accuracy and performance of next-generation processor designs. You will collaborate with architects, RTL developers, and physical design teams to verify CPU architectures powering millions of devices globally.

The role involves developing verification plans, building UVM-based testbenches, running system-level simulations, and debugging in a pre-silicon environment.

Qualifications

• Bachelor's, Master's, or PhD in EE/CE or related STEM with relevant experience.
• Strong SystemVerilog skills for UVM-based testbenches and timing analysis.
• Proficiency in Python or Perl for test automation and debugging; C++ knowledge.

Responsibilities

• Develop and execute verification plans to validate CPU logic against architectural specs.
• Build scalable UVM-based testbenches and robust functional coverage models.
• Run system-level simulations to uncover design bugs and ensure functional integrity.
• Debug and root-cause issues in the pre-silicon environment; implement corrective measures.
• Collaborate with CPU architects and RTL designers to verify features.
• Document verification strategies and lead technical reviews with design teams.

Skills

SystemVerilog

UVM testbenches

Python

Perl

C++

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related STEM

Master's degree in Electrical Engineering, Computer Engineering, or related STEM

PhD in Electrical Engineering, Computer Engineering, or related STEM

Tools

Synopsys VCS

Git

Job description

Intel Corporation in Austin, Texas, seeks a CPU Design Verification Engineer to ensure functional accuracy and performance of next-generation processor designs. You will collaborate with architects, RTL developers, and physical design teams to verify CPU architectures powering millions of devices globally.

The role involves developing verification plans, building UVM-based testbenches, running system-level simulations, and debugging in a pre-silicon environment.