SoC Design Intern: Verilog RTL for High-Performance SSDs

SK hynix memory solutions America Inc.; San Jose (CA); In loco; USD 48.000 - 62.000; Tempo pieno

Descrizione del lavoro

SK hynix memory solutions America is seeking an intern to join the SoC Design Team in San Jose. You will contribute to RTL design (Verilog/SystemVerilog) for IPs and collaborate with Verification, Silicon Validation, and Firmware teams to ensure design quality.

The role focuses on learning micro-architecture, RTL coding and documenting processes, with 40 hours/week work and an immediate start (Nov/Dec 2026) in a high-performance SSD storage environment.

Competenze

• Currently enrolled in BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and SystemVerilog language.

Mansioni

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Conoscenze

Logic design

Micro-architecture

RTL coding (Verilog/SystemVerilog)

Formazione

EE/CE student

Strumenti

Python

Perl

TCL

Linux

Descrizione del lavoro

SK hynix memory solutions America is seeking an intern to join the SoC Design Team in San Jose. You will contribute to RTL design (Verilog/SystemVerilog) for IPs and collaborate with Verification, Silicon Validation, and Firmware teams to ensure design quality.

The role focuses on learning micro-architecture, RTL coding and documenting processes, with 40 hours/week work and an immediate start (Nov/Dec 2026) in a high-performance SSD storage environment.