SoC ASIC Design Intern - RTL/Verilog (San Jose)

skhynixmemorysolutionsamericainc; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Job summary

SK hynix memory solutions America is seeking an internship in SoC design to join the System on Chip team. You will work on RTL design (Verilog/SystemVerilog) for IP used in high-performance SSD controllers, spanning the full design cycle from micro-architecture to tapeout readiness.

Qualifications include being enrolled in BS/MS/PhD in Electrical/Computer Engineering or related field, with RTL coding in Verilog/SystemVerilog and knowledge of AMBA, PCIe, NAND, and DDR.

Qualifications

• Enrolled in BS/MS/PhD program in Electrical or Computer Engineering or related field.
• RN RTL coding experience in Verilog/SystemVerilog.
• Strong logic design and micro-architecture skills.
• Knowledge of AMBA, PCIe, NAND and DDR.
• Proficient with Linux command-line interface.
• Scripting skills: Python, Perl, TCL.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specs.
• Collaborate with Design Verification, Silicon Validation, and Firmware teams; produce clear documentation.

Skills

RTL design

logic design

micro-architecture

Verilog

SystemVerilog

Linux CLI

Python

Perl

TCL

Education

BS/MS/PhD in Electrical/Computer Engineering or related

Tools

Verilog/SystemVerilog

AMBA

PCIe

NAND

DDR

Job description

SK hynix memory solutions America is seeking an internship in SoC design to join the System on Chip team. You will work on RTL design (Verilog/SystemVerilog) for IP used in high-performance SSD controllers, spanning the full design cycle from micro-architecture to tapeout readiness.

Qualifications include being enrolled in BS/MS/PhD in Electrical/Computer Engineering or related field, with RTL coding in Verilog/SystemVerilog and knowledge of AMBA, PCIe, NAND, and DDR.