ASIC Design Intern

skhynixmemorysolutionsamericainc; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Job summary

SK hynix memory solutions America is seeking an internship in SoC design to join the System on Chip team. You will work on RTL design (Verilog/SystemVerilog) for IP used in high-performance SSD controllers, spanning the full design cycle from micro-architecture to tapeout readiness.

Qualifications include being enrolled in BS/MS/PhD in Electrical/Computer Engineering or related field, with RTL coding in Verilog/SystemVerilog and knowledge of AMBA, PCIe, NAND, and DDR.

Qualifications

• Enrolled in BS/MS/PhD program in Electrical or Computer Engineering or related field.
• RN RTL coding experience in Verilog/SystemVerilog.
• Strong logic design and micro-architecture skills.
• Knowledge of AMBA, PCIe, NAND and DDR.
• Proficient with Linux command-line interface.
• Scripting skills: Python, Perl, TCL.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specs.
• Collaborate with Design Verification, Silicon Validation, and Firmware teams; produce clear documentation.

Skills

RTL design

logic design

micro-architecture

Verilog

SystemVerilog

Linux CLI

Python

Perl

TCL

Education

BS/MS/PhD in Electrical/Computer Engineering or related

Tools

Verilog/SystemVerilog

AMBA

PCIe

NAND

DDR

Job description

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change - we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Internship Duration:

6 months

Hours:

40 hours per week

Start Date:

Immediately (November 2026/December 2026)

Location:

San Jose

About The Role

You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle-from micro-architecture and RTL design to timing closure and tapeout readiness-enabling next-generation enterprise and AI data center storage solutions.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Minimum Qualifications

• Education: Currently enrolled in BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.

Preferred Qualifications

• Advanced Education: Master's or PhD in Electrical Engineering with working experiences.
• Experience or coursework in digital logic design, verification methodologies, and protocols (AMBA, PCIe, NAND, DDR)
• Scripting skills (Python, Perl, TCL) and Linux command-line experiences
• Strong problem-solving and communication skills
• Proficiency in AI tool to generate synthesizable and functional RTL code

COMPENSATION

$35/hr - $45/hr