SoC Architect

Volantis Semiconductor, Inc.; Boston (MA); On-site; USD 180,000 - 260,000; Full time

Job summary

Volantis Semiconductor, Inc. is seeking SoC architects to own the detailed SoC-level architecture of dies on wafer-scale systems. You will collaborate with architecture and ASIC design teams to draft specs and drive the execution of implementations.

The ideal candidate has proven ownership of at least one SoC/die, deep architecture–to–physical design understanding, and the ability to coordinate across multiple teams to deliver high-performance SoCs.

Qualifications

• Full ownership of specs and implementation for at least one SoC/die.
• Deep understanding of architecture, microarchitecture and physical design and ability to coordinate with various groups to drive implementation of SoCs.
• Ability to coordinate with packages, memory subsystems and IO blocks to drive SoC implementations.

Responsibilities

• Own the detailed SoC-level architecture and create implementable specs.
• Drive execution of SoC implementations with architecture and ASIC teams.

Skills

SoC architecture

die-level ownership

architecture coordination

microarchitecture understanding

physical design

memory subsystems

IO interfaces

multi-die design

reticle-max/large-die architecture

PPA optimization

high-speed silicon delivery

Job description

What We're Looking For:

We're looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations.

Ideal Background:

An ideal candidate will have:

• Experience with full ownership of the specs and drove implementation for at least one SoC/die
• A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs
• Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks

Nice to Have:

• Experience with multi-die/multi-chiplet/MCM designs
• Experience with reticle-max/large-die SoC architecture
• Understanding of levers available for improving PPA
• Track record of very high speed A0 silicon delivery