Architect- Subsystem

Volantis Semiconductor, Inc.

Boston (MA)

On-site

USD 120,000 - 180,000

Full time

14 days+
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Job summary

Volantis Semiconductor, Inc. is seeking architects to own key blocks on the A-0 and A-1 systems.

This role entails ownership of an entire sub-block and requires understanding how it fits into the complete system, with collaboration across architecture leaders to integrate it into the broader design. The ideal candidate has hands-on experience delivering block architectures within larger chips, experience with AI accelerators, and collaboration with microarchitects for implementation and

Qualifications

  • Own and deliver the architecture of a chip block that integrates into a larger system.
  • Hands-on experience designing AI accelerators and optimizing performance.
  • Collaborate with microarchitects to implement and verify the block within a full chip design.

Responsibilities

  • Own key blocks on the A-0 and A-1 systems and ensure correct integration into the broader system.
  • Coordinate with architecture leaders and other teams to align interfaces and verification plans.
  • Drive design decisions from block-level details to system-level implications.

Skills

Block architecture ownership
AI accelerators design
Microarchitecture collaboration

Job description

What We’re Looking For:

We’re looking for architects to own key blocks on the A-0 and A-1 systems. This is a role with ownership of an entire sub-block, and you will need to understand how it fits into the entire system and work with other architects and architecture leaders to integrate it into the broader system.

Ideal Background:
  • Hands-on experience in owning and delivering the architecture of a block that was part of a larger chip/system.
  • Understanding and hands-on experience in the design of AI accelerators
  • Experience working with microarchitects in the implementation and verification of said block
Nice to Have:
  • Experience with the physical design process of the block you owned
  • Experience with large die area chips
  • Experience with multi-die and multi-package chips and systems
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