Silicon CAD Tool Engineer – Chassis Automation

Intel; Santa Clara (CA); Hybrid; USD 150,000 - 211,000; Full time

Job summary

Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon Chassis Automation Tool team. In this hands‑on role, you will work closely with the tool lead to develop a chassis automation tool and own key subsystems.

The role involves collaborating with RTL design, verification, and SoC integration teams to codify architectural rules of the interconnect and to deliver a reliable, testable automation framework, with AI-assisted workflows embedded in day-to-day development.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or related field with 4+ years of CAD/EDA tooling or design automation, or a Master's degree in a related field with 3+ years.

Responsibilities

• Develop a chassis automation tool that meets requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility.
• Understand automation tool requirements and build tooling to translate those requirements into working code, generating outputs such as RTL, RDL, verification collateral, timing, and integration artifacts.
• Integrate with silicon frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (RTL, Verilog, SDC, RDL).
• Work closely with the tool lead and design/verification/integration teams to ensure outputs meet downstream expectations.
• Set up and maintain CI/CD regression pipelines and write unit tests to extend coverage.

Skills

Python

Git

CI/CD

JSON schemas

OO design

Education

Bachelor's degree in Electrical Engineering, Computer Science, or related field

Tools

CAD/EDA tooling

Design automation frameworks

SystemVerilog

NoC architectures

IP packaging (IP-XACT)

GUI frameworks (Qt/QML)

Job description

Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon Chassis Automation Tool team. In this hands‑on role, you will work closely with the tool lead to develop a chassis automation tool and own key subsystems.

The role involves collaborating with RTL design, verification, and SoC integration teams to codify architectural rules of the interconnect and to deliver a reliable, testable automation framework, with AI-assisted workflows embedded in day-to-day development.