Silicon Architect & RTL Designer - High-Perf Compute

MatX; Mountain View (CA); Hybrid; USD 160,000 - 600,000; Full time

Benefits offered by this job

PTO 4 weeks

12 company holidays

Up to 3 weeks remote work

Health insurance

401k

Team lunch/dinner

Commuting reimbursement

Job summary

MatX in Mountain View, CA is building a scalable silicon platform for GenAI workloads. We seek silicon micro-architects and design engineers to own subsystems from architecture to tapeout, delivering high-performance, power-efficient silicon.

You will collaborate closely with verification, DFT and physical design teams, drive design reviews, and ensure timing, area and power goals are met across milestones in a hybrid work model.

Qualifications

• SystemVerilog, Python, C/C++ for chip design and related flows
• Silicon architecture and design concepts for CPUs/GPUs/accelerators
• Verification collaboration and performance/coverage closure
• Design synthesis, clock-domain-crossing, linting
• DFT and physical design concepts and methodologies
• Experience with silicon debug and bring-up

Responsibilities

• Contribute to silicon architecture-to-design methodology across blocks, subsystems, fullchip
• Own subsystem or chip-level silicon design deliverables from micro-architecture to sign-off
• Plan and drive design reviews on micro-architecture, execution progress, area and timing
• Collaborate with verification, DFT and physical design co-owners to achieve best-in-class results

Job description

MatX in Mountain View, CA is building a scalable silicon platform for GenAI workloads. We seek silicon micro-architects and design engineers to own subsystems from architecture to tapeout, delivering high-performance, power-efficient silicon.

You will collaborate closely with verification, DFT and physical design teams, drive design reviews, and ensure timing, area and power goals are met across milestones in a hybrid work model.