Signal & Power Integrity Engineer—2.5D/3D-IC Packaging

Amazon; Cupertino (CA); On-site; USD 177,000 - 247,000; Full time

Job summary

Amazon Annapurna Labs is looking for a Signal or Power Integrity Engineer to join our Cupertino hardware team. You will perform package‑level SI/PI analyses for 2.5D/3D‑IC packaging and run high‑speed simulations to support die, package, and board interfaces.

You will build and validate decoupling models, coordinate with SoC and board teams, and help mitigate manufacturing risks while working with mentorship and advanced tools.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of experience in signal integrity, power integrity, or package design.
• Strong knowledge of SI or PI with cross-domain awareness.
• Experience with EM simulation and SI/PI tools (HFSS, Sigrity, ADS).
• Understanding of 2.5D/3D-IC, fan-out packaging, RDL, TSVs.
• Good communication across silicon, package, and board teams.

Responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan‑out, and interposer architectures.
• Support package stack‑up design: dielectric evaluation, impedance analysis, layer assignment, RDL routing.
• Run high‑speed channel simulations for die‑to‑die and die‑to‑board interfaces; analyze PDN performance.
• Model interconnects: microbumps, TSVs, RDL traces for signal/power paths.
• Build and validate decoupling models (on‑die capacitance, DTCs, IPD capacitors).
• Coordinate with SoC and board teams to co‑optimize package architecture.
• Flag manufacturing risks and propose mitigations.

Skills

SI knowledge

PI knowledge

Package design

EM simulation

HFSS

Sigrity PowerSI

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

HFSS

Cadence Sigrity PowerSI

Clarity

ADS

Job description

Amazon Annapurna Labs is looking for a Signal or Power Integrity Engineer to join our Cupertino hardware team. You will perform package‑level SI/PI analyses for 2.5D/3D‑IC packaging and run high‑speed simulations to support die, package, and board interfaces.

You will build and validate decoupling models, coordinate with SoC and board teams, and help mitigate manufacturing risks while working with mentorship and advanced tools.