Remote SI/PI Technical Leader for ASIC Packaging

Cisco Systems; Bismarck (ND); Hybrid; USD 190,000 - 360,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Paid time off and sick leave

Job summary

Cisco Systems in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to drive ultra-high-speed signaling, SI/PI for next-generation ASIC packaging, and to lead a cross-functional silicon packaging team.

The role requires extensive experience with 56G PAM4, high-speed SerDes, 2.5D packaging, and design-rule development. Hybrid on-site work with remote options are available.

Qualifications

• Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 8+ years of relevant signal and/or power integrity experience, or PhD in Electrical Engineering and 5+ years of relevant signal and/or power integrity experience.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters.
• Hands‑on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• We are seeking a highly qualified Signal and Power Integrity Technical Leader to help us develop our next generation ASIC packaging and lead our Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Skills

Signal integrity

Power integrity

ASIC packaging

Silicon packaging

High-speed signaling

SPICE

Lab experience

MATLAB/Python scripting

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

Job description

Cisco Systems in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to drive ultra-high-speed signaling, SI/PI for next-generation ASIC packaging, and to lead a cross-functional silicon packaging team.

The role requires extensive experience with 56G PAM4, high-speed SerDes, 2.5D packaging, and design-rule development. Hybrid on-site work with remote options are available.