SerDes Validation Engineer — High-Speed Lab & FPGA

Synopsys, Inc.; Hillsboro, Northern (OR, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Synopsys, Inc. in Hillsboro, OR seeks an engineer to validate high-speed SerDes PHYs in a hands-on R&D lab. You will run and debug tests, build test boards, and automate data collection while collaborating with analog designers to interpret results.

The role emphasizes lab skills, Verilog FPGA programming, and experience with NRZ/PAM4 signaling and protocol tests across USB, PCIe, SATA, and Ethernet.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• Solid understanding of analog IC circuit design and behavior, especially in high-speed mixed-signal environments.
• Strong debugging skills spanning silicon, hardware, firmware, and test setup.
• Hands-on experience with lab equipment including oscilloscopes, network analyzers, signal generators, and power supplies.
• Software programming experience in MATLAB, Python, or similar for test automation and data analysis.
• FPGA programming knowledge using Verilog for test pattern generation and protocol control.
• Familiarity with high-speed interface protocols such as USB, PCIe, SATA, or Ethernet is a strong plus.
• Experience with NRZ and PAM4 signaling, equalization techniques, or SerDes architecture is a plus.
• Knowledge of communication interfaces like JTAG, I2C, and SPI for device control and configuration.

Responsibilities

• Test silicon implementations of high-speed SerDes PHYs using state-of-the-art lab equipment including oscilloscopes, network analyzers, and signal integrity tools.
• Debug silicon behavior and supporting hardware when test results do not match expectations, tracing issues across the analog circuit, test board, and measurement setup.
• Run characterization tests across PVT corners and operating conditions, then create detailed test reports that communicate results to design and product teams.
• Design and build custom test boards and hardware solutions to support bring-up, debug, and characterization of new PHY IP.
• Program FPGAs in Verilog to generate test patterns, control interfaces, and automate test sequences for protocols like USB, PCIe, SATA, and Ethernet.
• Write test automation scripts in Python or MATLAB to streamline data collection, analysis, and reporting.
• Collaborate with analog designers to investigate circuit behavior, apply theoretical knowledge to explain performance limits, and validate design assumptions in silicon.

Skills

SerDes experience

FPGA Verilog

Python

MATLAB

Lab testing

Oscilloscopes

Network analyzers

Signal integrity

Debugging

Analog IC design

Education

Bachelor's degree in Electrical Engineering

Tools

Verilog

MATLAB

Python

Oscilloscopes

Network analyzers

Job description

Synopsys, Inc. in Hillsboro, OR seeks an engineer to validate high-speed SerDes PHYs in a hands-on R&D lab. You will run and debug tests, build test boards, and automate data collection while collaborating with analog designers to interpret results.

The role emphasizes lab skills, Verilog FPGA programming, and experience with NRZ/PAM4 signaling and protocol tests across USB, PCIe, SATA, and Ethernet.