SerDes IP Systems Engineering Director

Cadence

San Jose (CA)

On-site

USD 179,000 - 332,000

Full time

5 days ago
Be an early applicant
Application generator

Turn this role into an interview — a resume and cover letter built around what this employer wants.

Get past ATS filters

Benefits offered by this job

Bonus
Equity
Benefits

Job summary

Cadence invites a Systems Engineering Director to lead the Die-to-Die Interface IP team within the Silicon Solutions R&D Group. You will drive system-level analyses, set SerDes specifications, and mentor engineers while contributing hands-on in development.

The role emphasizes modeling, algorithm development, and collaboration with customers and cross-functional teams to push the performance of D2D SerDes IP. A PhD or MS is required, with 10+ years in high-speed SerDes and related areas.

Qualifications

  • PhD or MS in Electrical/Computer Engineering (or similar degree).
  • Strong background in high-speed SerDes and PHYs.

Responsibilities

  • Key contributor and driver of the R&D team that defines, models and analyzes high performance D2D SerDes IP microarchitecture, link budget and specifications.
  • Develop infrastructure to ensure robust product development, systems modeling analysis and testing.
  • Develop statistical and linear systems analysis of the link, model nonidealities and determine design specifications for circuit designers.
  • Develop and provide guidelines regarding signal integrity and power integrity to customers.
  • Support customer package/board design and debug as necessary.
  • Guide the package design team based on in-package D2D link channel analysis.
  • Generate technical specification, data sheets, and application notes.
  • Update R&D team with the latest standards developments, customer feedback and competitive analysis.

Skills

D2D SerDes architecture
System-level analysis
Signal processing (DSP)
Leadership

Education

PhD in Electrical/Computer Engineering
MS in Electrical/Computer Engineering

Tools

Matlab
Perl

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is a unique opportunity to join the rapidly growing Die-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems. We are looking for a Systems Engineering Director who will be a key driver and contributor to the development of our advanced D2D SerDes IP products. This role involves leading the D2D Systems analysis team as well as contributing with hands on technical development.

Main Job Tasks and Responsibilities:
  • Key contributor and driver of the R&D team that defines, models and analyzes high performance D2D SerDes IP microarchitecture, link budget and specifications
  • Develop infrastructure to ensure robust product development, systems modeling analysis and testing
  • Develop statistical and linear systems analysis of the link, model nonidealities and determine design specifications for circuit designers
  • Develop and provide guidelines regarding signal integrity and power integrity to customers
  • Support customer package/board design and debug as necessary
  • Guide the package design team based on in-package D2D link channel analysis
  • Generate technical specification, data sheets, and application notes
  • Update R&D team with the latest standards developments, customer feedback and competitive analysis
Position Requirements:
  • PhD or M.S. in Electrical/Computer Engineering (or similar degree)
  • 10+ years of experience working with high speed high performance SerDes and PHYs
  • The ability to think through engineering systems end-to-end and identify bottlenecks and weak points.
  • Strong mathematical skills, in particular relating to linear systems (Fourier analysis, filter theory, etc.)
  • Deep understanding of high speed SerDes architecture
  • Deep knowledge of communication systems fundamentals and wireline communications
  • Strong coding skills for simulation and modelling, as well as data analysis
  • Good knowledge of signal processing (DSP) algorithms and architecture.
  • Good working knowledge of physics of signal propagation
  • Good working knowledge of basic circuits
  • Experience generating systems or IBIS-AMI models
  • Experience using system simulation tools, especially Matlab, Perl, and other scripting tools
  • Demonstrated capacity to self-educate themselves to pick up new fields of expertise
  • D2D link experience is preferred but not required
  • Familiarity with emerging D2D standards such as UCIe is desired
  • Strong debug and problem-solving skills
  • Must have strong group presentation and leadership skills.
  • Ability to clearly communicate technical challenges and status to customers, team members, senior management and executives
  • Familiarity with advanced technology nodes (7nm and below) is a plus
  • Experience with 3D electromagnetic simulation tools is a plus

The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

High Speed PHY FW Engineer
High Speed PHY FW Engineer

Cadence • San Jose (CA)

On-site
USD 101,000 - 189,000
Principal Analog I.C Engineer
Principal Analog I.C Engineer

Cadence • San Jose (CA)

On-site
USD 137,000 - 254,000
401(k) match
Employee stock purchase plan
Medical, dental, and vision plans
+2
SerDes IP Systems Engineering Director Cadence
SerDes IP Systems Engineering Director Cadence

Semiconductor Engineering • San Jose (CA)

Hybrid
USD 190,000 - 270,000
Director, SerDes IP Systems & D2D Architecture
Director, SerDes IP Systems & D2D Architecture

Cadence • San Jose (CA)

On-site
USD 179,000 - 332,000
Bonus
Equity
Benefits
SerDes IP Systems Engineering Director
SerDes IP Systems Engineering Director

Cadence Design Systems • San Jose (CA)

On-site
USD 179,000 - 332,000
Sr Principal Design Engineer
Sr Principal Design Engineer

Cadence • San Jose (CA)

On-site
USD 154,000 - 286,000
Paid vacation
401(k) plan with employer match
Employee stock purchase plan
+1
SERDES IP SYSTEMS ENGINEERING DIRECTOR
SERDES IP SYSTEMS ENGINEERING DIRECTOR

Semiconductor Engineering • San Jose (CA)

On-site
USD 180,000 - 260,000
Sr. Principal Product Engineer
Sr. Principal Product Engineer

Cadence • California (MO)

On-site
USD 144,000 - 267,000
Bonus potential
Equity
Benefits package
Mixed-Signal, Sr Principal Design Engineer
Mixed-Signal, Sr Principal Design Engineer

Cadence • San Jose (CA)

On-site
USD 154,000 - 286,000
Sr Principal Engineer -SIPI
Sr Principal Engineer -SIPI

Cadence Design Systems • San Jose (CA)

Hybrid
USD 154,000 - 286,000
401(k) match
Employee stock purchase plan
Medical/Dental/Vision coverage