Director, SerDes IP Systems & D2D Architecture

Cadence; San Jose (CA); On-site; USD 179,000 - 332,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence invites a Systems Engineering Director to lead the Die-to-Die Interface IP team within the Silicon Solutions R&D Group. You will drive system-level analyses, set SerDes specifications, and mentor engineers while contributing hands-on in development.

The role emphasizes modeling, algorithm development, and collaboration with customers and cross-functional teams to push the performance of D2D SerDes IP. A PhD or MS is required, with 10+ years in high-speed SerDes and related areas.

Qualifications

• PhD or MS in Electrical/Computer Engineering (or similar degree).
• Strong background in high-speed SerDes and PHYs.

Responsibilities

• Key contributor and driver of the R&D team that defines, models and analyzes high performance D2D SerDes IP microarchitecture, link budget and specifications.
• Develop infrastructure to ensure robust product development, systems modeling analysis and testing.
• Develop statistical and linear systems analysis of the link, model nonidealities and determine design specifications for circuit designers.
• Develop and provide guidelines regarding signal integrity and power integrity to customers.
• Support customer package/board design and debug as necessary.
• Guide the package design team based on in-package D2D link channel analysis.
• Generate technical specification, data sheets, and application notes.
• Update R&D team with the latest standards developments, customer feedback and competitive analysis.

Skills

D2D SerDes architecture

System-level analysis

Signal processing (DSP)

Leadership

Education

PhD in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Matlab

Perl

Job description

Cadence invites a Systems Engineering Director to lead the Die-to-Die Interface IP team within the Silicon Solutions R&D Group. You will drive system-level analyses, set SerDes specifications, and mentor engineers while contributing hands-on in development.

The role emphasizes modeling, algorithm development, and collaboration with customers and cross-functional teams to push the performance of D2D SerDes IP. A PhD or MS is required, with 10+ years in high-speed SerDes and related areas.