Principal Analog I.C Engineer

Cadence; San Jose (CA); On-site; USD 137,000 - 254,000; Full time

Benefits offered by this job

401(k) match

Employee stock purchase plan

Medical, dental, and vision plans

Paid vacation & holidays

Bonus & equity

Job summary

Cadence in California seeks a Principal Analog IC Designer responsible for designing and developing analog/mixed-signal circuit blocks from concept through verification, ensuring conformance to customer specifications.

Candidates should have 7+ years in CMOS SerDes or high-speed I/O, strong jitter and SI knowledge, Cadence CAD tools expertise, and MS or PhD in EE; salary range and benefits are provided. Collaborate with teams to meet performance goals and schedules.

Qualifications

• Minimum of 7 years in CMOS SerDes or high-speed I/O IC design.
• Jitter and signal equalization techniques understood.
• Cadence tool experience, lab test experience, and >10Gbps and <28nm design experience a plus.
• MS or PhD in EE.

Responsibilities

• Design and develop analog/mixed-signal IC blocks from concept to verification.
• Ensure conformance to customer specifications through final verification.
• Collaborate with cross-functional teams and use CAD tools for simulation and layout.

Skills

CMOS SerDes Design

High-speed I/O

Jitter & signal integrity

Analog/mixed-signal design

Circuit simulation

Lab/test experience

Team collaboration

Education

MS or PhD in EE

Tools

Cadence CAD tools

Layout & physical verification tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

• Candidate's background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development
• Working knowledge of a set of common SerDes standards and their electrical requirements is a plus
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification
• Cadence tool experience, lab test experience, and design experience at >10Gbps and in <28nm technologies are a plus
• MS or PhD in EE

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.