SerDes Design & Validation Lead

Apple Inc.; Austin, Northern (TX, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. is seeking a SerDes Design and Validation Engineer to lead system validation of mixed-signal SerDes IP. You will design and validate high-speed receivers, transmitters, bias generators, and clock networks, aiming for best-in-class power, performance, and area.

You will develop analog DFT techniques, create test plans, and collaborate with production test teams to debug bring-up issues. The role requires strong fundamentals, curiosity, and leadership in a collaborative, diverse

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Experience in high-speed serial links and SerDes protocols (PCIe, USB, DP, MPHY) preferred.
• Knowledge of Tx/Rx equalization, CTLE, DFE, de-emphasis, CDR architectures.
• Experience with AMS IC development and layout supervision.

Responsibilities

• Ownership of SerDes system bring-up, validation and debug.
• Define DFT needs to improve testability and first-time silicon success.
• Collaborate with design teams to understand architecture and enable testability.
• Drive lab and production testing, data analysis and issue debug.

Skills

SerDes design

Analog/mixed-signal

High-speed SerDes

DFT/test development

AMS IP development

Lab testing

Automation scripting

Education

Bachelor's degree in Electrical Engineering

Tools

Python scripting

EDA tools

Lab instrumentation

Job description

Apple Inc. is seeking a SerDes Design and Validation Engineer to lead system validation of mixed-signal SerDes IP. You will design and validate high-speed receivers, transmitters, bias generators, and clock networks, aiming for best-in-class power, performance, and area.

You will develop analog DFT techniques, create test plans, and collaborate with production test teams to debug bring-up issues. The role requires strong fundamentals, curiosity, and leadership in a collaborative, diverse