Senior SerDes System Validation Engineer – High-Speed Links

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 185,000 - 325,000; Full time

Benefits offered by this job

Apple stock programs

Relocation assistance

Educational expense reimbursement

Job summary

Apple Inc. in Cupertino, California, is seeking a SerDes System Validation Engineer to lead system validation of mixed-signal SerDes IP across SoC and PHY contexts.

You will collaborate with Analog-Mixed/Signal design teams to validate embedded circuits and ensure first-time silicon success while delivering high-quality IP for Apple’s products. Ownership of SerDes bring-up, validation and debug, plus defining DFT needs and working with design teams to analyze robustness and margins.

Qualifications

• BS and 10+ years industry experience or equivalent.
• 1
• Experience with high-speed SerDes validation and bring-up.

Responsibilities

• Ownership of SerDes system bring-up, validation and debug.
• Define DFT needs to enable testability and first-time silicon success.
• Collaborate with design teams for architecture understanding and verification.

Skills

SerDes validation

Mixed-signal verification

Scripting

High-speed protocols

Lab bring-up

C/ Matlab / Python

PCB familiarity

Communication skills

Debugging

Education

BS in Electrical Engineering

Tools

Python

C

Matlab

Job description

Apple Inc. in Cupertino, California, is seeking a SerDes System Validation Engineer to lead system validation of mixed-signal SerDes IP across SoC and PHY contexts.

You will collaborate with Analog-Mixed/Signal design teams to validate embedded circuits and ensure first-time silicon success while delivering high-quality IP for Apple’s products. Ownership of SerDes bring-up, validation and debug, plus defining DFT needs and working with design teams to analyze robustness and margins.