Senior Wireless RTL Design Engineer – Energy-Efficient SoCs

Apple, Inc.; Irvine (CA); On-site; USD 175,000 - 309,000; Full time

Benefits offered by this job

Medical & dental

Retirement benefits

Product discounts

Tuition reimbursement

Bonuses/commissions

Relocation

Job summary

Apple Inc. in Irvine, CA is seeking a senior hardware design engineer to join the wireless silicon development team. You will develop signal processing intensive designs for wireless SOCs with emphasis on energy efficiency and fast delivery to hundreds of millions of customers.

Responsibilities include writing specifications from MATLAB/C models, RTL design and verification support, lint-free design checks, and collaborating with algorithm and software teams to optimize performance and power.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Fixed-point knowledge and bit-true verifications.
• Understanding of DSP communication algorithms and trade-offs.
• Knowledge in energy-efficient/low-power design.
• Ability to work well in a team under aggressive schedules.
• Excellent communication skills and self-motivated.

Responsibilities

• Writing specifications and documents based on MATLAB/C system models.
• RTL logic design and verification support.
• Running tools to ensure lint-free design.
• Collaborating with algorithm and software teams to optimize performance and power.

Skills

MATLAB/C system model

Fixed-point

DSP algorithms

Energy-efficient design

Team collaboration

Communication skills

Education

BS

Tools

Synthesis tools

CDC tools

Power analysis

Job description

Apple Inc. in Irvine, CA is seeking a senior hardware design engineer to join the wireless silicon development team. You will develop signal processing intensive designs for wireless SOCs with emphasis on energy efficiency and fast delivery to hundreds of millions of customers.

Responsibilities include writing specifications from MATLAB/C models, RTL design and verification support, lint-free design checks, and collaborating with algorithm and software teams to optimize performance and power.