Senior Wireless SoC Design Engineer

Apple, Inc.; Sunnyvale (CA); On-site; USD 185,000 - 325,000; Full time

Job summary

Apple seeks an experienced ASIC design engineer to join its wireless silicon team in Sunnyvale. You will design CPU-based subsystems for high performance, low power wireless SoCs, collaborating with architects, IP developers, and platform engineers to meet power, area, and performance goals.

You will write micro-architecture specs, code RTL in SystemVerilog, integrate IP blocks, optimize memories and macros, and assist verification while using static tools to ensure quality and timely delivery

Qualifications

• BS with 10+ years relevant experience.
• Familiarity with the ASIC design flow.
• Knowledge of digital design, SoC architecture, and HDL languages like Verilog.

Responsibilities

• Writing micro-architecture and design specifications.
• Coding design in SystemVerilog following established guidelines, owning RTL development.
• Integrate IP blocks and optimize memories/hard macros for the block.
• Supporting verification efforts at multiple levels.
• Checking your design with static tools such as LINT, CDC, RDC.
• Analyzing and optimizing area, timing, and power.
• Collaborate with multi-disciplinary groups to ensure timely, high-quality delivery with proper checks.

Skills

Digital design

SoC architecture

Verilog

Power optimization

Education

BS in Electrical Engineering or related field

Tools

SystemVerilog

LINT

CDC

RDC

EDA tools

Job description

Apple seeks an experienced ASIC design engineer to join its wireless silicon team in Sunnyvale. You will design CPU-based subsystems for high performance, low power wireless SoCs, collaborating with architects, IP developers, and platform engineers to meet power, area, and performance goals.

You will write micro-architecture specs, code RTL in SystemVerilog, integrate IP blocks, optimize memories and macros, and assist verification while using static tools to ensure quality and timely delivery