Power-Efficient Wireless SoC Design Engineer

Apple, Inc.

Sunnyvale (CA)

On-site

USD 129,000 - 225,000

Full time

30 hours ago
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Benefits offered by this job

Medical and dental coverage
Retirement benefits
Employee stock programs
Tuition reimbursement

Job summary

Apple, Inc. is seeking a power management logic engineer for its wireless silicon development team in Sunnyvale, CA. You will design power management logic for complex wireless SoCs and contribute to energy-efficient designs that impact hundreds of millions of customers.

The role requires a bachelor’s degree and strong experience in Verilog, power/clock/reset management, and debugging. Collaboration with cross-functional teams and post-silicon activities are key parts of the job.

Qualifications

  • Bachelor’s degree required.
  • Experience in power/clock/reset management logic design.
  • Proficiency in Verilog.
  • Experience in power management logic verification and debugging.
  • Understanding ASIC low power design techniques (CDC, RDC, STA, UPF).
  • Proficiency in scripting languages (Shell, Perl, Python).
  • Knowledge of common SoC components (CPU, fabric, peripherals).
  • Strong problem solving and analytical skills.

Responsibilities

  • Define SoC power management features to meet product requirements.
  • Implement power management logic.
  • Collaborate with XF teams to verify power management logic.
  • Support Power team on power analysis and post-silicon correlation efforts.
  • Post silicon bring up and debug support.

Skills

Power/clock/reset management
Verilog
Scripting (Shell/Perl/Python)
Debug and verification
System on Chip knowledge

Education

Bachelor’s degree

Tools

Verilog

Job description

Apple, Inc. is seeking a power management logic engineer for its wireless silicon development team in Sunnyvale, CA. You will design power management logic for complex wireless SoCs and contribute to energy-efficient designs that impact hundreds of millions of customers.

The role requires a bachelor’s degree and strong experience in Verilog, power/clock/reset management, and debugging. Collaboration with cross-functional teams and post-silicon activities are key parts of the job.

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