Low Power SoC Design Engineer - Power Management Expert

Apple, Inc.; Irvine (CA); In loco; USD 175.000 - 309.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical coverage

Dental coverage

Retirement benefits

Stock programs

Tuition reimbursement

Relocation

Descrizione del lavoro

Apple in Irvine, CA is seeking a senior engineer to design power management logic for complex wireless SOCs. You will define features, implement logic, and work with verification teams to ensure low power operation across products used by millions of customers.

The role requires a BS in a relevant field, 10+ years of experience in power/clock/reset design, Verilog proficiency, and strong analytical skills. Relocation assistance may be provided.

Competenze

• BS and a minimum of 10 years relevant industry experience.
• Proven track record in power / clock / reset management logic design.
• Proficiency in Verilog language.
• Power management logic verification and debug experience.
• Understand ASIC low power design techniques.
• Knowledge of CDC, RDC, STA and UPF.
• Proficiency in scripting languages (Shell, Perl or Python).
• Knowledge and experience on common SOC components, e.g. CPU, fabric, peripherals.
• Strong problem solving and analytical skills.

Mansioni

• Define SoC power management features to meet product requirements.
• Implement power management logic.
• Work with XF teams to verify power management logic.
• Support Power team on power analysis and post-silicon correlation efforts.
• Post silicon bring up and debug support.

Conoscenze

Power management design

Verilog

Scripting

Problem solving

ASIC low power

Formazione

Bachelor's degree

Descrizione del lavoro

Apple in Irvine, CA is seeking a senior engineer to design power management logic for complex wireless SOCs. You will define features, implement logic, and work with verification teams to ensure low power operation across products used by millions of customers.

The role requires a BS in a relevant field, 10+ years of experience in power/clock/reset design, Verilog proficiency, and strong analytical skills. Relocation assistance may be provided.