Senior Wireless IP & RTL Design Engineer

International Association of Plumbing and Mechanical Officials (IAPMO); Irvine, Northern (CA, KY); Hybrid; USD 110,000 - 160,000; Full time

Job summary

We are seeking a Design Engineer to join an elite team focused on wireless communications, developing IP, system, and board solutions that advance 5G capabilities. This hands-on role involves shaping our product portfolio and actively contributing to architecture, design, verification, and documentation of IP RTL implementations using SystemVerilog.

The ideal candidate has 4+ years of industry experience, strong proficiency with EDA tools (ModelSim, Quartus, Vivado, Synopsys DC, Cadence Genus),

Qualifications

• 4+ years of relevant industry experience.
• Experience with EDA tools for simulation and synthesis.
• AXI interfacing experience.
• Timing and hardware resource optimization for high throughput signal processing.
• Prototyping in C/C++/Matlab for design and verification.
• Solid version control practices (Git) and documentation habits (Confluence).
• Bonus: EDA tooling admin experience, automation (Jenkins), or knowledge of communications signal processing (error correction, equalization, channel estimation, beamforming).

Responsibilities

• Architecture, design, development, verification and documentation of IP RTL implementations using SystemVerilog.
• Testbench development for RTL implementations.

Skills

IP RTL design

Testbench development

SystemVerilog

C/C++/Matlab prototyping

Version control (Git)

Documentation (Confluence)

Education

Bachelor's degree or higher

Tools

ModelSim

Quartus

Vivado

Synopsys DC

Cadence Genus

Jenkins

Git

Job description

We are seeking a Design Engineer to join an elite team focused on wireless communications, developing IP, system, and board solutions that advance 5G capabilities. This hands-on role involves shaping our product portfolio and actively contributing to architecture, design, verification, and documentation of IP RTL implementations using SystemVerilog.

The ideal candidate has 4+ years of industry experience, strong proficiency with EDA tools (ModelSim, Quartus, Vivado, Synopsys DC, Cadence Genus),