Design Engineer

International Association of Plumbing and Mechanical Officials (IAPMO); Irvine, Northern (CA, KY); Hybrid; USD 110,000 - 160,000; Full time

Job summary

We are seeking a Design Engineer to join an elite team focused on wireless communications, developing IP, system, and board solutions that advance 5G capabilities. This hands-on role involves shaping our product portfolio and actively contributing to architecture, design, verification, and documentation of IP RTL implementations using SystemVerilog.

The ideal candidate has 4+ years of industry experience, strong proficiency with EDA tools (ModelSim, Quartus, Vivado, Synopsys DC, Cadence Genus),

Qualifications

• 4+ years of relevant industry experience.
• Experience with EDA tools for simulation and synthesis.
• AXI interfacing experience.
• Timing and hardware resource optimization for high throughput signal processing.
• Prototyping in C/C++/Matlab for design and verification.
• Solid version control practices (Git) and documentation habits (Confluence).
• Bonus: EDA tooling admin experience, automation (Jenkins), or knowledge of communications signal processing (error correction, equalization, channel estimation, beamforming).

Responsibilities

• Architecture, design, development, verification and documentation of IP RTL implementations using SystemVerilog.
• Testbench development for RTL implementations.

Skills

IP RTL design

Testbench development

SystemVerilog

C/C++/Matlab prototyping

Version control (Git)

Documentation (Confluence)

Education

Bachelor's degree or higher

Tools

ModelSim

Quartus

Vivado

Synopsys DC

Cadence Genus

Jenkins

Git

Job description

We're hiring: Design Engineer

Join an elite team working at the cutting edge of wireless communications technology, developing IP, system, and board solutions that push the capabilities of 5G forward.

This is a hands on role where you'll play a real part in growing our product portfolio, not just executing someone else's roadmap.

What you'll work on:

• Architecture, design, development, verification and documentation of our IP RTL implementations of communication electronics systems using SystemVerilog
• Testbench development for RTL implementations

What we're looking for:

• 4+ years of relevant industry experience, degree qualified
• EDA tools for simulation and synthesis (ModelSim, Quartus, Vivado, Synopsys DC, Cadence Genus)
• AXI interfacing experience
• Timing and hardware resource optimization for high throughput signal processing
• C/C++/Matlab prototyping for design and verification
• Solid version control practices (Git) and documentation habits (Confluence)
• Bonus points for EDA tooling admin experience, automation (Jenkins), or knowledge of communications signal processing (error correction, equalization, channel estimation, beamforming)

We're looking for someone highly capable, motivated, and commercially savvy, someone who builds trust quickly and communicates clearly across technical and non technical stakeholders alike.

If you want to help shape the next generation of global wireless connectivity, this is your seat at the table.